The SFG-Tracing methodology [5] addresses the automatic verification of digital synchronous circuit implementations as specified at the algorithmic level as signal-(SFG) or data flow graphs. The SFG-Tracing methodology is a multi-level design verification paradigm that aims at bridging the gap between higher level specifications down to lower level implementations up to the transistor switch level. In this paper the concepts of the SFG-Tracing methodology are illustrated by the automatic verification of a transistor level implementation of a small chip generated from its high level specification by the CATHEDRAL-I1 silicon compiler. This application, although simple, includes a datapath, register files, a multi-branch micro coded controller, and additional circuitry as necessary for Design for Testability measures. This application illustrates the SFG-Tracing verification methodology as applied to one member of a partitioned SFG behavioral specification. Experimental results on more complex, completely verified designs of 32000 transistors demonstrate the feasibility of the approach.
This paper presents the application of partially ordered strength sets, as introduced by Agrawal et.al., within the symbolic switch-level analysis of digital MOS circuits, where until now only a straightforward approach using a total ordering was used. The paper gives a mathematical formulation for the analysis. The method has been implemented within the ezisting switch-level analyzer ANAMOS and has been applied successfully to practical circuits.
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