For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, ...) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO 2 hard mask may lead to severe profile distortions, attributed to TiF x compounds which settle on the trenches sidewalls. A chuck temperature of 60°C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.
International audiencePorous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) can lead to an extrinsic roughening mechanism, such as micromasking caused by metallic particles originating form the titanium nitride mask
The etching of sub-100-nm porous dielectric trenches has been investigated using an organic mask. The etching process that is performed in an oxide etcher is composed of three steps: a thin dielectric antireflective coating (DARC) layer (silicon containing layer) is etched in the first step, the organic mask [carbon-based layer (CL)] is opened in the second step, and the dielectric layer is etched in the last step. The DARC layer is open in a fluorocarbon-based plasma (CF4∕Ar∕CH2F2) and the main critical dimension issue is the critical dimension control of the trench, which can be adjusted by controlling the amount of polymer generated by the etching chemistry (% of CH2F2). The CL is etched using NH3 based plasmas, leading to straight trench profiles. For dielectric patterning, the etch process results from a delicate trade-off between passivation layer thickness and mask faceting. This is driven by the polymerizing rate of the plasma (% of CH2F2) which controls the trench width. Using an optimized etching process (CF4∕Ar∕2%CH2F2), p-SiOCH trenches can be patterned with straight etch profiles down to 75nm trench width. In this article, the authors have also compared the organic mask and TiN metal hard mask strategies in terms of patterning performances (profile control, porous SiOCH modification, and reactor wall cleaning processes).
With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasmainduced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures.We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.
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