System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to hardware, a significant improvement in task switching times can be achieved. This paper presents a custom designed multi pipeline register architecture (MPRA) that has a dedicated hardware scheduler unit integrated into the CPU.
Infrastructure underlying the distributed information systems is heterogeneous and very complex. Middleware allows the development of distributed information systems, without knowing the functioning details of an infrastructure, by its abstracting. An essential issue on designing such systems is represented by choosing the middleware technologies. An architectural model of a SCADA system based on middleware is proposed in this paper. This system is formed of servers that centralize data and clients, which receive information from a server, thus allowing the chart displaying of such information. All these components own a specific functionality and can exchange information, by means of a middleware bus. A middleware bus signifies a software bus, where more middleware technologies can coexist
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