Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers &amp;#x2014; Concept and theory of operation

Dodiu, Eugen; Găitan, Vasile Gheorghiţă

doi:10.1109/eit.2012.6220705

Cited by 25 publications

(17 citation statements)

References 10 publications

(14 reference statements)

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“…The current paper extends the processor architecture presented in [3] and [4], implementing original new solution for the nMPRA and nHSE real-time behavior. The scheduler architecture has been implemented with a dynamic algorithm, providing predictability and hardware based isolation for the HT.…”

Section: Discussionmentioning

confidence: 99%

“…This architecture implemented for n tasks, called Fine-grained Multithreading -Multi Pipeline Register Architecture (nMPRA-MT), extends the Multi Pipeline Register Architecture (MPRA) project presented in [3] and [4]. This concept replaces the stack saving classical method with a remapping algorithm, which uses the replication of resources such as program counter, register file and pipeline registers, for n threads, τ n , as shown in Fig.…”

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

“…The nMPRA-MT architecture has the interrupt system presented in [3]. This interrupt handling is completely distributed and flexible in the system, allowing us to prevent the unpredictable situations generated by the interrupt service routines (ISRs).…”

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

“…Gaitan et al present in [9] the basics of the nMPRA architecture for n tasks using the remapping algorithm with the replication of resources. Thus, each task scheduled by the nHSE has a distinct program counter (PC), a separated bank in the Register file, and a distinct set of pipeline registers (IF/IDInstruction Fetch-Instruction Decode stage, ID/EX -Instruction Decode-Execute stage, EX/MEM -Execute-Memory stage, and MEM/WB -Memory-Write Back stage).…”

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

See 3 more Smart Citations

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Gaitan¹,

Zagan²,

Găitan³

2015

ijacsa

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Abstract-The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.

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Section: Discussionmentioning

confidence: 99%

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

Section: The Fine-grained Nmpra-mt Architecturementioning

confidence: 99%

See 2 more Smart Citations

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Gaitan¹,

Zagan²,

Găitan³

2015

ijacsa

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“…The function contexts saving and the parameters transmission are performed in a similar way to that in the case of classic MIPS processors. The bank selection is performed in hardware, the operation being independent of instructions executed at the level of each sCPUi [6].…”

Section: Nmpra Architecture and Hardware Supportmentioning

confidence: 99%

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

Zagan¹,

Gaitan²,

Găitan³

2017

ijacsa

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Abstract-One of the fundamental requirements of real time operating systems is the determinism of executing critical tasks and treating multiple periodic or aperiodic events. The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization and inter-task communication mechanisms. Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental results obtained using Virtex-7 FPGA circuit. The article's element of originality is the very short response time required in treating and prioritizing events.

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Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Zagan

Găitan

2023

IEEE Access

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In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where n is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for n threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper propose an innovative soft-core implementation to reduce interrupt latencies, while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system which allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture's predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.INDEX TERMS Hardware RTOS, microprocessor, scheduling, field-programmable gate arrays (FPGA), real-time systems

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Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Cited by 25 publications

References 10 publications

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

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