2015
DOI: 10.14569/ijacsa.2015.060406
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Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Abstract: Abstract-The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obta… Show more

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Cited by 6 publications
(3 citation statements)
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“…The disadvantage of the proposed algorithm for implementing the StartTaskServerMBECycle task is that it relatively has many lines of pseudocode and it transfers the actual tasks of reading/writing data, executing Modbus messages and configuration to the StartTaskServerMBEProtocol task. Thus, the algorithm can be improved to allow a better evaluation of the message processing time relative to the total execution time of the microcontroller [ 38 ].…”
Section: Proposed Modbus Extension Server Implementationmentioning
confidence: 99%
“…The disadvantage of the proposed algorithm for implementing the StartTaskServerMBECycle task is that it relatively has many lines of pseudocode and it transfers the actual tasks of reading/writing data, executing Modbus messages and configuration to the StartTaskServerMBEProtocol task. Thus, the algorithm can be improved to allow a better evaluation of the message processing time relative to the total execution time of the microcontroller [ 38 ].…”
Section: Proposed Modbus Extension Server Implementationmentioning
confidence: 99%
“…We remind that all sCPUi share the same functional units, such as ALU, the control unit, the condition unit, the unit for hazard detection, and the redirection of data unit, so that the data path must guarantee the hardware isolation and the consistency of sCPUi contexts [16]. At a 33MHz frequency, the scheduler answer to an time related event may be around 30.401ns (one clock cycle).…”
Section: Fig 2 the Registers Of The Nhse Hardware Integrated Schedulermentioning
confidence: 99%
“…The nMPRA-MT architecture presented in [27] is a finegrained multithreaded processor based on the original nMPRA concept, designed to support architectural requirements for hard real-time systems.…”
Section: B Proposed Nmpra-mt Architecturementioning
confidence: 99%