Abstract:A 9-bit 11GS/s DAC is presented that achieves an SFDR of more than 50dB across Nyquist and IM3 below -50dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these subDACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04mm 2 while consuming 110mW from a single 1.0V supply.
A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 11GS/s, occupying only 0.04mm2 and consuming 110mW from a single 1V supply. Conventional CS DACs are limited in performance by static and dynamic errors; the latter typically limit high speed performance. The main dynamic errors are due to the output capacitance of the current sources, signal dependent supply and bias loading effects and other switching related errors. Techniques such as additional cascodes with bleeding current sources [1] and return-to-zero switching schemes can suppress some of these errors, but they have their own specific drawbacks. Here quad-switching [2] is combined with interleaving [3] to suppress the dominant dynamic errors in CS DACs.Interleaved architecture The architecture of the interleaved CS DAC is shown in Fig. 1; it shows the two parallel sub-DACs (sDACs) that operate out of phase and shows the analog multiplexer that toggles the outputs of each sDAC between the overall DAC output and a dummy output. The sDACs are conventional CS DACs, consisting of many current sources and their accompanying switches (slices) in parallel. During the time an sDAC is connected to the dummy output it switches to its next code. Since the dynamic errors of a CS DAC are centered around the code switching moment, these errors are dumped on the dummy output and hence do not propagate to the overall DAC output. Once these errors are sufficiently stabilized, the analog multiplexer connects the sDAC to the output, after which the second sDAC switches to its next code while being connected to the dummy output. This way each sDACs runs at half the sampling clock, with out-of-phase clocks for the two sDACs. Although interleaved DACs use multiple sub-DACs that all consume power and area, the significantly lower demands on timing and settling in the individual sDACs allows to design overall power and area efficient DACs.For sufficiently high spurious-free dynamic range (SFDR) , the dynamic effects on the bias and power supply lines also must be sufficiently small and must be code-independent. The interleaving structure already allows for extra settling time, while we also implemented quad-switching [2] to ensure code-independent switching activity. Quad-switching uses four switches for one sDAC slice, two at the positive output and two at the negative output. Of these four switches, only one switch is on in each sample interval. In each new sample interval, another switch will be turned on; the code determines whether that switch is connected to the positive or the negative output. Overall this yields code independent dynamic load on both the power supply and on the bias voltages. In a regular CS DAC employing quad-switch...
A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below-62dB across Nyquist with a clock frequency of 1.7GHz. The circuit's active area is 0.4mm 2 and the power consumption is 70mW from a nominal 1.2V supply. I.
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