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Delphi-like boundary condition independent (BCI) compact thermal models (CTMs) are the standard for modelling single die packages. However their extraction, particularly in the transient case, will be time consuming due to complex numerical simulations for a large number of external conditions. Lately, new approaches to extract a BCI dynamical CTM (DCTM), based on model order reduction (MOR) were developed. Despite the numerous advantages of this recent method, the lack of numerical tools to integrate reduced-order models (ROM) makes it difficult to use at board level. In this study, a novel process flow for extracting Delphi-inspired BCI DCTMs is proposed. Thus a detailed three-dimensional model is replaced by a BCI-ROM model using FANTASTIC matrix reduction code to generate the data used in the creation of a Delphi-style BCI DCTM. That hybrid reduction method has been applied, at first on a single-chip package (QFN16) then on a dual-chip package (DFN12). Their derived CTM and DCTM have been compared in term of accuracy and creation time using, or not, MOR reduction technique. The results show that for a similar accuracy, the integration of MOR technique allows minimizing the time-consuming numerical simulations and consequently reduce the thermal network creation time by 80%.

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The recent Printed Wiring Board embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple layers of embedded chips. This disruptive technology will further increase the thermal management challenges by concentrating heat dissipation at the heart of the organic substrate structure. In order to allow the electronic designer to early analyze the limits of the power dissipation, depending on the embedded chip location inside the board, as well as the thermal interactions with other buried chips or surface mounted electronic components, an analytical thermal modelling approach was established. The presented work describes the comparison of the analytical model results with the numerical models of various embedded chips configurations. The thermal behaviour predictions of the analytical model, found to be within ±10% of relative error, demonstrate its relevance for modelling high density electronic board. Besides the approach promotes a practical solution to study the potential gain to conduct a part of heat flow from the components towards a set of localized cooled board pads

Nowadays a high-level integration with unprecedented functionality and efficient performances is achieved through 3D packaging techniques known as System-In-Package (SIP). The paper describes the reduction process conducted on a realistic SIP module case in order to establish a behavioral thermal network having a large number of power sources. Besides this device has been slightly modified to focus on the recent 3D integration techniques such as the stacking of chip, multi-chips side by side architecture or the embedding of conventional individually-packaged Integrated Circuits (IC). These works compared the prediction of a DELPHI style Compact Thermal Model (CTM)[1][6] to a numerical Detailed Thermal Model with for aim to illustrate the diminution of computation delays, the expected accuracy and some efficient ways to improve it.Then it describes the performance of a novel methodology that nests a set of Sub-Compact Thermal Models (SCTM) within the detailed numerical model, far less grid-intensive, and its ability to preserve the final SIP CTM quality.