2018
DOI: 10.1016/j.microrel.2018.06.009
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Multi-port dynamic compact thermal models of dual-chip package using model order reduction and metaheuristic optimization

Abstract: Delphi-like boundary condition independent (BCI) compact thermal models (CTMs) are the standard for modelling single die packages. However their extraction, particularly in the transient case, will be time consuming due to complex numerical simulations for a large number of external conditions. Lately, new approaches to extract a BCI dynamical CTM (DCTM), based on model order reduction (MOR) were developed. Despite the numerous advantages of this recent method, the lack of numerical tools to integrate reduced-… Show more

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Cited by 21 publications
(6 citation statements)
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References 19 publications
(29 reference statements)
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“…The dual-chip architecture separates the parts that are prone to interfere with each other, which can effectively reduce noise and improve the resolution of the sensor [ 21 ], at the same time, Brice.R et al . [ 22 ], used a model reduction method to analyze the heat dissipation problem of the dual-chip architecture and experimentally verified that the dual-chip architecture can reduce the thermal network creation time by 80%. Therefore, the dual-chip architecture has stronger thermal and immunity capabilities and is more suitable for high-speed mechanical platforms.…”
Section: Literature Reviewmentioning
confidence: 99%
“…The dual-chip architecture separates the parts that are prone to interfere with each other, which can effectively reduce noise and improve the resolution of the sensor [ 21 ], at the same time, Brice.R et al . [ 22 ], used a model reduction method to analyze the heat dissipation problem of the dual-chip architecture and experimentally verified that the dual-chip architecture can reduce the thermal network creation time by 80%. Therefore, the dual-chip architecture has stronger thermal and immunity capabilities and is more suitable for high-speed mechanical platforms.…”
Section: Literature Reviewmentioning
confidence: 99%
“…As seen in Figure 8, the chip is now partitioned in nine zones (2 9 possible combinations) to model more accurately the heating due to the individual activation of various logical functions. The largest source and the smallest one represent respectively 22.4% and 1.8% of the chip volume.…”
Section: Impact Of Chip Power Dissipation Layoutmentioning
confidence: 99%
“…The reduced model is obtained by reducing the initial base by the amalgam method [7]. These developments gave birth to a new hybrid methodology to build DELPHI-inspired DCTMs by replacing the full detailed models by a reduced-order model based on the modal approach [8,9]. However, more complex configurations demand more sophisticated methods, in which simple reduced models are built and then connected to each other.…”
Section: Introductionmentioning
confidence: 99%
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“…Krylov subspace-based MOR techniques have been utilised for thermal analysis of an electric converter assembly by Liu et al [7]. Thermal boundary condition independency of Krylov subspace-based reduced order modelling approach has been examined for thermal and coupled thermal analysis by Rogié et al [8] and Codecasa et al [9,10].…”
Section: Introductionmentioning
confidence: 99%