The etching of Si, SiO 2 , Si 3 N 4 , and SiCH in fluorocarbon plasmas is accompanied by the formation of a thin steady-state fluorocarbon film at the substrate surface. The thickness of this film and the substrate etch rate have often been related. In the present work, this film has been characterized for a wide range of processing conditions in a high-density plasma reactor. It was found that the thickness of this fluorocarbon film is not necessarily the main parameter controlling the substrate etch rate. When varying the self-bias voltage, for example, we found a weak correlation between the etch rate of the substrate and the fluorocarbon film thickness. Instead, for a wide range of processing conditions, it was found that ion-induced defluorination of the fluorocarbon film plays a major role in the etching process. We therefore suggest that the fluorocarbon film can be an important source of fluorine and is not necessarily an etch-inhibiting film.

Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential of this process for circuit relevant patterning continues to be a major challenge. In this work, we propose a way to impart two-dimensional pattern information in graphoepitaxy-based lamellar phase DSA processes by utilizing the interactions of the BCP with the template pattern. The image formation mechanism is explained through the use of Monte Carlo simulations. Circuit patterns consisting of the active region of Si FinFET transistors, referred to as Si "fins", were fabricated to demonstrate the applicability of this technique to the formation of complex patterns. The quality of the Si fin features produced by this process was validated by demonstrating the first functional DSA-patterned FinFET devices with 29 nm-pitch fins.

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated. Introduction Phase change memory (PCM) is widely considered to be a potential next-generation non-volatile solid-state memory [1-3]. In addition to its superior write speed compared to 0.2pm -flash, PCM offers a large signal margin between its -crystalline and amorphous states. This wide dynamic range Fig. 2: TEM image of phase-change element (PCE), with underlying also opens the door for multi-level cells (MLC). In this paper, TiN heater on top of W contact. The phase-change material and the we explore MLC write algorithms for up to 16 levels in small o T test arrays, and then demonstrate a 4-level, 32kbit page being overln Tiner are coNnected ubinEs thr a via.part of an experimental memory chip. transferred into the TiN layer using RIB. After strip, oxide isolation is deposited and planarized, exposing the top of the Integration Scheme pillar electrode. The Ge2Sb2Te5 and TiN top electrode layers The memory cell consists of a pillar-heater phase change are then deposited, patterned into islands and encapsulated element (PCE) in series with an access nMOSFET (180nm with dielectric. Top contacts and metallization lines are CMOS technology). As shown in Fig. 1, the 50nm bottom formed using a standard Cu damascene process. Fig. 2 shows electrode heater is fabricated in a subtractive process from a a TEM cross-section of the finished pillar-heater PCE. 75nm thick TiN layer directly deposited over the W contacts.

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with <100µA RESET current. The device concept provides for simplified scaling to small crosssectional area (60nm 2 ) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention.