Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

Standaert, T. E. F. M.; Hedlund, Christer; Joseph, Eric; Oehrlein, G. S.; Dalton, T.

doi:10.1116/1.1626642

Cited by 244 publications

(153 citation statements)

References 13 publications

(10 reference statements)

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“…[100][101][102] Due to differences in dry etch selectivity and other considerations to be discussed later, a-SiO 2 , a-Si 3 N 4 , and related a-SiN:H complement one another and make an excellent choice as the ILD and DB in Cu interconnect structures. [103][104][105][106] However as mentioned above, insulators are needed with dielectric permittivity values substantially less than that of PECVD SiO 2 (k = 4.0-4.4) and PECVD a-SiN:H (k = 6.5-7.0) to reduce RC delays in advanced interconnect structures. To meet this need, low-k a-SiOC:H ILDs and a-SiCN:H DBs with dielectric permittivity values of 3.0-3.2 and 5.5-5.8, respectively, were introduced and implemented by the semiconductor industry in the early-mid 2000's.…”

Section: Low-k Ild Cu Cumentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: Low-k Ild Cu Cumentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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“…fairly rapid etching for one material and slow etching or deposition for another material. [20][21][22][23][24][25][26] However, the thicknesses of these steady-state surface layers can be of the order of several nm. During the time needed for these to form, significant material loss can take place.…”

mentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

ECS J. Solid State Sci. Technol.

Self Cite

223

162

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The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

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“…In comparing the bond strengths, the Si-O bond had a higher binding energy (192 kcal/mol) than that of the Si-N bond (105 kcal/mol) [13]. The low binding energy of the Si-N bond has long been accepted as the reason for the higher etch rate of Si 3 N 4 over crystalline SiO 2 ceramics [14]. In our study, however, the nitrogen incorporation into the oxynitride glass lowered the etch rate under fluorine plasma, via a mechanism that can be explained in terms of the glass structure.…”

Section: Discussionmentioning

confidence: 98%

Effects of nitrogen incorporation on plasma erosion behaviors of oxynitride glasses

Lee

Hwang

Lee

et al. 2010

Journal of Non-Crystalline Solids

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Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide

Cited by 244 publications

References 13 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Atomic Layer Etching at the Tipping Point: An Overview

Effects of nitrogen incorporation on plasma erosion behaviors of oxynitride glasses

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