The crystalline silicon heterojunction structure adopted in photovoltaic modules commercialized as Panasonic's HIT has significantly reduced recombination loss, resulting in greater conversion efficiency. The structure of an interdigitated back contact was adopted with our crystalline silicon heterojunction solar cells to reduce optical loss from a front grid electrode, a transparent conducting oxide (TCO) layer, and a-Si:H layers as an approach for exceeding the conversion efficiency of 25%. As a result of the improved short-circuit current (J sc ), we achieved the world's highest efficiency of 25.6% for crystalline silicon-based solar cells under 1-sun illumination (designated area: 143.7 cm 2 ).

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We evaluated the conduction mechanisms and temperature dependence of HIT (heterojunction with intrinsic thin layer) structure solar cells while changing the thickness of the undoped amorphous silicon layer. It was confirmed that the diffusion model determined the carrier transport property of this device at the high-forward-bias region (0:4 < V < 0:8 V), whereas the multistep tunneling model determined the current transport at the low-bias region (0:1 < V < 0:4 V). The insertion of the high-quality hydrogenated amorphous silicon (a-Si:H) i-layer is very important for suppressing the probabilities of tunneling through the localized states in a-Si:H and surface recombination velocity at the heterointerface. The better temperature dependence of output power of HIT structure solar cells than that of the crystalline silicon (c-Si) homojunction solar cell is caused mainly by the high-open circuit voltage that originates in the effectively suppressed saturation current with HIT structure, and also by the fill factor (F.F.), which is affected by the change in conductivity in the a-Si:H i-layer.

We have achieved a very high conversion efficiency of 21Á5% in HIT cells with a size of 100Á3 cm 2 . One of the most striking features of the HIT cell is its high opencircuit voltage V oc , in excess of 710 mV. This is due to the excellent surface passivation at the a-Si/c-Si heterointerface realized by Sanyo's successful technologies for fabricating high-quality a-Si films and solar cells with low plasma damage processes. We have studied ways to treat the surface to produce a good interface throughout our fabrication processes. We have also investigated the deposition conditions of a-Si layers for optimizing the barrier height for the minority carriers in the heterojunction. Our approach for obtaining HIT cells with a high V oc is reviewed here.