Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for More than Moore solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven open TSV technology on the basis of a 0.35m CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35m CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxi de layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35m CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250m and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the op
The ATHENIS_3D FP7 EU project aims at providing new enabling technologies (analog, digital and power components) for high-voltage and high-temperature applications, tested for power systems of new hybrid/electrical vehicles. Innovation is exploited at process/device level (3D chip stacking, wafer level packaging, trench capacitors and TSV-inductors integrated in the interposer, high-reliable non-volatile Magnetic RAM), circuitlevel (inductorless high-voltage DC DC converter, hightemperature 28nm System-on-Chip platform) and system-level (compact 3D embedded power mechatronic system). Enabling high integration levels of complex systems, operating in harsh environments, in a single packaged 3D device, ATHENIS_3D allows for one order of magnitude area reduction vs. today PCBbased power and control systems. Integration costs will be consequently reduced in key industrial sectors for Europe where high-voltage/temperature operations are mandatory (vehicles, avionics, space/defence, industrial automation, energy).
Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics.HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded nonvolatile memory.In this work we propose a new 0.35 mm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 mm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM=Flash technology is shown.We also provide first verification results of the scalability of the proposed 0.35 mm HVCMOS technology to 0.18 mm and beyond as well as to currents of up to 8 A.Skalierbare Hochvolt-CMOS-Technologie fü r ,,Smart Power''-und Sensoranwendungen. Die Integration von analogen und digitalen Funktionen bei immer niedrigeren Versorgungsspannungen sowie deren Kombination mitHochvolt-Bauelementen mit Betriebsspannungen von deutlich mehr als 5 V sowie hoher Strombelastbarkeit ermö glicht den Aufbau von ,,Smart Power-Schaltkreisen'', die in modernen elektronischen Systemen nicht mehr wegzudenken sind. HVCMOS(Hochvolt-CMOS)-Technologien ermö glichen bei -im Vergleich zu BCD-Technologien -wesentlich geringeren Herstellungskosten verschiedene HVSpannungsebenen auf einem Chip, sie zeichnen sich auch durch leichte Skalierbarkeit aus, weiters kö nnen nichtflü chtige Speicher einfach integriert werden.In dieser Arbeit wird eine neue 0,35-m-HVCMOS-Technologie vorgestellt, die die bisherigen Grenzen bei der Stromergiebigkeit ü berwindet. Es sind mit BCD vergleichbare Chip-Grö ßen und Rdson-Werte mö glich, dennoch werden nur zwei zusä tzliche Masken benö tigt. Es werden eine Leistungskennzahl fü r den Vergleich solcher Prozesse vorgestellt und die wesentlichen Erfolgsfaktoren dieser Entwicklung diskutiert. Wesentliche Wettbewerbsfaktoren sind dabei eine Lebensdauer von > zehn Jahren, Betriebstemperaturen von 150 C und eine ESD-Festigkeit von >4 kV HBM sowie die Integration eines robusten EEPROM=Flash-Speichers. Es werden auch erste Ergebnisse der Skalierung der Bauelemente nach 0,18 m und kleiner sowie Resultate fü r die Steuerung von Strö men bis zu 8 A dargestellt.
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