We briefly review the status of the application of carbon nanotubes (CNTs) for future interconnects and present results concerning possible integration schemes. Growth of single nanotubes at lithographically defined locations (vias) has been achieved which is a prerequisite for the use of CNTs as future interconnects. For the 20 nm node a current density of 5·10 8 A/cm 2 and a resistance of 7.8 kΩ could be achieved for a single multi-walled CNT vertical interconnect.

Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10-30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 10(7). The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 microm, and decreased exponentially for gate lengths exceeding 1 microm.

A comparison of different catalysts (Ni, Co, Fe/Mo) has been performed in order to minimize the growth temperature for single-walled carbon nanotubes (SWCNTs). Dense SWCNT networks have been synthesized by thermal chemical vapor deposition (CVD) at temperatures as low as 600 °C using Ni catalyst layers of approximately 0.2 nm thickness. The dependence of the SWCNT growth on the most important parameters will be discussed exemplarily on the Ni catalyst system. On the basis of experimental observations, a phenomenological growth model for CVD synthesis of SWCNTs is proposed which is based on the interactions between the catalyst and its support. Further, it is suggested that only surface diffusion of hydrocarbons on the catalyst support or along the CNTs can explain the fast growth rates of SWCNTs during CVD synthesis.

Planar field effect transistors (FET) consisting of a large number of parallel single-walled carbon nanotubes (SWCNT) have been fabricated that allow very high on-currents of the order of several milliamperes and on/off ratios exceeding 500.With these devices it is demonstrated, for the first time, that SWCNTs can be used as transistors to control macroscopic devices, e.g., light emitting diodes and electromotors. Those transistors were fabricated by a very simple process that is based on the catalytic chemical vapor deposition (CCVD) growth of SWCNTs at low temperatures, a single lithographic step to define the source and drain contacts, and a bias pulse to eliminate the metallic SWCNTs.There has been tremendous interest in carbon nanotubes in the past decade 1 due to their superior electronic properties and the possibility that they could replace silicon in future nanoelectronic devices if the integration challenges can be solved. However, carbon nanotubes are also interesting for applications where larger currents have to be switched or detected, e.g., power transistors, flexible electronics, or sensors. Since the maximum current per individual SWCNT is limited to about 25 µA, 2 a parallel arrangement of a large number of SWCNTs is required. Fabrication of such an arrangement requires a process to grow or deposit SWCNTs uniformly on a substrate. Catalytic CVD allows the growth of very clean, amorphous carbon-free SWCNTs on substrates and the control over the density of active catalytic sites and, therefore, the density of the SWCNTs. Control of the SWCNT density is very important in order to achieve transistors with uniform performance, for reasons discussed below. Extensive studies of the CVD growth have shown that this can be achieved by varying the catalyst material, catalyst layer thickness, and the growth parameters. Those results have been published elsewhere. 3,4 The substrate for the SWCNT transistors was p-type silicon with a 50 nm thick atomic-layer-deposited (ALD) Al 2 O 3 with a k-value of about 11. Nickel was chosen as the catalyst metal, since it has been shown that Ni catalyzes the thermal CVD growth of SWCNTs at temperatures as low as 600°C. 5 Ni layers with a nominal thickness of less than 0.2 nm were deposited by a high-precision ion-beam deposition system with a quartz crystal microbalance or by spinon deposition of an ethanol-based nickel-acetate solution. 4 The SWCNTs were grown in a preheated quartz tube furnace at 650°C. After 5-10 min hydrogen pretreatment the growth was initiated by filling the furnace with pure methane to a pressure of 0.3-0.4 bar. After 10 min the growth was stopped by evacuating the furnace and the samples were removed from the furnace after cooling-down to room temperature. Subsequently, the transistors, shown in Figure 1, were defined by e-beam lithography whereby the gap between source and drain, which defines the gate length, was varied ( Figure 2). The smallest gate length was about 90 nm. The total gate width, which is equal to the circumference of the inner ...

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