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INTRODUCTIONOne of the promising technologies under development for next generation non-volatile memory is the Conductive Bridging Random Access Memory (CBRAM) which utilizes the reversible switching of an electroresistive dielectric between two conductive states as means of storing logical data [1][2][3][4][5]. In this paper, we describe the successful integration of CBRAM technology into an industry standard logic process. Moreover, we show functional operation of such a fully CMOS integrated CBRAM memory array and highlight its specific fundamental low power characteristics that make it suitable to be used in scaled embedded application as well as discrete devices. BACKGROUND AND EXPERIMENTSCBRAM technology is known by other names such as programmable metallization cell (PMC) solid electrolyte memory, nano-ionic resistive memory, electrochemical memory (ECM). The operational principle of CBRAM technology is based on a reversible creation of an electrochemically induced nanoscale conductive link in a special dielectric acting as a ion conducting solid-electrolyte. In its simplest implementation, the basic storage element consists of an access transistor and a programmable resistor (similar to the DRAM one transistor and one capacitor cell). We have successfully integrated this resistive memory in 180nm with Aluminum back-end-of-line (BEOL) as well as 130nm with Copper BEOL logic processes ( Fig. 1 & 2). Cross section image of a fully integrated 1T1R cells are shown in these figures. The programmable elements required only 2 non critical masks at BEOL steps. In this paper, we present basic characterization results on 180nm and 130nm logic CMOS integrated CBRAM memory arrays. We explore the operational capability of the core technology including sub 100ns write, data sheet operation at 1V, multi-level cell capability as well as retention and reliability characteristics. Data was collected on single cells as well as fully integrated decoded arrays. RESULTS AND DISCUSSIONThe DC or quasi static current voltage characteristics in Fig. 3 shows that as the voltage across the storage resistor is swept, the device is initially at high resistance state and switches on upon reaching a certain threshold voltage. Here, a current compliance of 10μA prevents the resistance to increase in a runaway effect. When the voltage is swept back, the storage dielectric is shown to be in the conductive state. A dynamic range of 10,000 is shown in this graph. This conductive state is a function of the program current and can be controlled accurately rendering multi-level cell possibility for this technology. Figure 3b shows the dependence of resistance state on programming current. This allows for potential use of this technology in multi-level cell (MLC) implementation. The threshold voltage can be tuned by process and operational parameters to fit seamlessly in a standard logic process. To erase the cell, the voltage is swept back in the negative direction and the high resistance state is recovered.A critical aspects of a new technology...

High-temperature data retention is a critical hurdle for the commercialization of emerging nonvolatile memories. For Conductive-Bridge RAM (CBRAM) [1], we discuss hightemperature retention in terms of the physics of quantum point contacts, and we report on a family of CBRAM cells that achieve excellent retention at temperatures exceeding 200ºC.