Grain-bondary erosion-type voids and transgranular slit-like voids are found to be two competing electromigration failure modes in VLSI interconnects. The effects of interconnect linewidth, microstructure, process variables and stress conditions on the two failure modes were studied.
Grain-boundary (GB) erosion-type voids and transgranular slit-like voids are found to be two competing elecaomigration (EM) failure modes in partly-bamboo interconnects. The effects of metal microstructure, passivation thickness, line width and length, and EM sbess conditions on the two failure modes were studied. The kinetics for GBtype failures is strongly affected by the threshold effect in polycrystalline segments and is well described by the MultiLognormal (MLN) function with stress-dependent number of elements. The model @cts that the EM resistance of partly-bamboo lines at VLSI operating conditions is limited by the slit failure mode, rather than by GB-type failures.not only time is saved, but the statistical error brackets are reduced. The problem of Joule heating can be alleviated by optimizing the test " r e layout.In this work, we evaluated the effect of line length on the parameters of the failure time distribution. 1 mm long lines were typically used to characterize the EM kinetics and the effect of process variables for wider, partly-bamboo lines, while 14 mm or 19 mm long lines were used to characterize narrow, bamboo lines. The effect of linewidth on EM lifetime was studied for both 1 mm and 14 mm long lines.The experimental results are interpreted in terms of the MLN model. The effect of material characteristics and EM stress conditions on the model parameters is discussed.
EXECUTIVE SUMMARYThe effect of stress conditions on the electromigration degradation mode of TiN-layered A1 interconnects is discussed. Interconnect lifetime improves dramatically when Al-0.15%Ti alloy is used instead of Al-l%Si-O.l5%Ti. A TIN underlayer reduces an A1 alloy EM resistance, unless the TiN is exposed to air prior to A1 deposition.
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