A parallel processor for real-time motion estimation algorithms has been developed. It consists of several clusters of basic processing elements connected to a transfer controller that is attached to an external RAM. The architecture is parallel, allowing each cluster to work on non-overlapping image segments. It is also associative, in that the execution of a global instruction step by a processing element depends on some local conditions; moreover, lateral communications between clusters are provided, these two last features being essential for motion vector field regularization processes. Feasibility of the architecture has been evaluated with an advanced block-matching based motion estimation algorithm: the ABMA. Running at a clock rate of 50MHz, a group of 12 processing elements can real-time execute the ABMA on a Common Input Format (CIF) image (288 >< 352 pixels, at 10Hz). A custom VLSI test circuit, consisting of one processing element and one transfer controller has been designed in a 1 pm technology; the total silicon area of the test circuit is 41 mm2.
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