The XC8100 FFGA family is based on a new metal-to-metal antifuse technology and a "sea-of-gates'' type architecture. Programmable interconnect elements are stacked vertically between metal layers and above the fine-grained logic cells, resulting in small die sizes and low cost. The basic cell is designed specifically for technology-independent design. Each cell can be configured to implement combinatorial, sequential, or three-state buffering functions. Other architectural features include a flexible set of high-drive buffers, output slew rate controls, and PCI-compatible IiO structures. A patented programming and test structure addresses the problem of providing for 100% post-program verification without test vectors.
IntroductionThe evolution of Field Programmable Gate Array (FPGA) technology has been characterized by continuing increases in capacity and decreases in cost per gate. In an FPGA, both capacity and cost are direct functions of the silicon area required to implement the logic cells and their programmable interconnections. Traditionally, the logic elements and programmable interconnect have competed for the same silicon area. In the XC8100 FPGA architecture, the programmable interconnect is vertically stacked above the logic cells using the MicroViaTM technology; the new MicroVia technology combines a three-layer-metal CMOS process, a metal-to-metal antifuse programming element, and a sea-ofgates architecture. The combination of these three elements allows the development of FPGAs with extensive routing resources and high gate utilization in a very small die size.
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