In today's highly competitive market, system designers are faced with the conflicting challenges of greater system complexity and the need for short, efficient design cycles. These complexity and time-to-market pressures continue to reshape the art of designing electronic systems, and have led to the emergence and growing acceptance of top-down design methodologies and logic synthesis tools. With top-down design, engineers start work at a higher-level of abstraction than with traditional, gate-level design techniques. The designer manipulates logical or functional abstractions, and uses logic synthesis tools to produce the gate-level implementation. Over the past decade, topdown design has become increasingly popular for the design of gate array and custom cell devices. As the density and complexity of FPCA-based designs has increased to 10,ooO gates and beyond, users are now employing the same techniques and similar tools for FPGA design. The use of logic synthesis for P G A design will continue to accelerate as ever-larger FPGA devices are introduced.Logic synthesis tools are the keystone of top-down design methodologies. In general, logic synthesis is the process of generating an optimized gate-level netlist for a logic design from some higher-level structural description. A much narrower definition that reflects the current stateof-the-art describes logic synthesis as an automated process that translates a register-transfer-level (RTL) description of a digital system, usually written in a highlevel hardware description language such as VHDL or Verilog-HDL, into a gate-level netlist targeted for implementation in a specific ASIC architecture. Typically, logic synthesis is a two-step process: level translation and logic optimization. Level translation refers to the mapping of the RTL circuit description into a gate-level netlist for the target ASIC architecture. During the optimization phase, the tool searches for equivalent circuits that will reduce the area or increase the performance of the actual implementation. For example, if the target architecture is a Complex PLD with AND-OR plane logic, the optimization step would involve finding the simplest sum-of-products representation for the circuit's logic functions. Once synthesis is completed, architecture-specific layout tools, such as placement and routing tools for FPGAs, are required to complete the implementation of the circuit.Two main types of hardware description languages for programmable logic are in use today. "Single-modulelevel HDLs" typically are used to describe small modules within a schematic-based hierarchical design; examples include PALASM, ABEL", and CUPL@. These languages (and the earliest commercial synthesis tools) were developed to support the PAL@-like programmable logic devices of the late 1970s. "System-level HDLs" that support more complex constructs and higher levels of abstraction emerged in the 1980s; the most popular system-level HDLs are VHSIC-HDL (VHDL) and Verilog-HDL. System-level HDLs are modular, in that large designs ca...
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