Louic emulation is a technique that uses dvnamically TepTogrammable systems for prototyping ad design verification.Usina an emulator. desianers can realize designs through a" software co&gun&on process and peTform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shodening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to Teplace portions of the design with macro cells. This paper presents a module generator foT logicemulation a.pplications, which is able to generate macro
cells of arbitrarily complex functions described in Highlevel Descriptive Languages (HDLs). Furthermore, the module geneTutor can effectively generate a multiple-FPGA macro fOT large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are TepOTted. The Tesults demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Tkansfer-Level (RTL) description.In addition, the Tesults also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.