According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1][2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTIrelated technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.In our work, a small pixel with fully surrounding and full-depth DTI is demonstrated. As shown in Fig. 7.1.1, in the conventional 2-dimensional (2D) pixel structure, if DTI is placed along the periphery of each pixel, the effective photodiode area is reduced by the amount of DTI width in addition to the fixed pixel transistor area. In a pixel size near 1.0μm, there is little area remaining for a photodiode and full-well capacity. In this paper, to overcome the small photodiode fill factor by the presence of DTI, a vertical transfer gate (VTG) and buried photodiode are combined with front DTI technology, forming a 3-dimensional (3D) pixel, which is realized in a single wafer, contrary to the previous silicon stack structure [7]. In this 3D pixel, transistors and photodiode are separated. Transistors are present in the silicon surface plane, as in conventional 2D pixels, but the photodiode is placed and buried beneath the transistor plane. A VTG connects both planes (photodiode and transistors) and thus accumulated charges in the bur...
