In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.
Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.
When a active sonar signal is transmitted and returned back from a target, it has been distorted by various properties of acoustic channel such as multipath arrivals. And signals have been appeared to be different form by target position and attitude. Therefore, we simulated the target echo signal using 3 dimensional target model include reflects target features. In this paper, we develop components form of a simulated target model is made up equally spaced highlight points, and each part of the target consists of shape function. We can simulate a target echo signal and Target strength (TS) according to wave incident angle. To verify, we made small scale target in kit form and we had got underwater target signal for comparing simulation result in water tank.
An extreme ultraviolet (EUV) pellicle is an ultrathin membrane at a stand-off distance from the reticle surface that protects the EUV mask from contamination during the exposure process. EUV pellicles must exhibit high EUV transmittance, low EUV reflectivity, and superior thermomechanical durability that can withstand the gradually increasing EUV source power. This study proposes an optimal range of optical constants to satisfy the EUV pellicle requirements based on the optical simulation results. Based on this, zirconium disilicide (ZrSi2), which is expected to satisfy the optical and thermomechanical requirements, was selected as the EUV pellicle candidate material. An EUV pellicle composite comprising a ZrSi2 thin film deposited via co-sputtering was fabricated, and its thermal, optical, and mechanical properties were evaluated. The emissivity increased with an increase in the thickness of the ZrSi2 thin film. The measured EUV transmittance (92.7%) and reflectivity (0.033%) of the fabricated pellicle satisfied the EUV pellicle requirements. The ultimate tensile strength of the pellicle was 3.5 GPa. Thus, the applicability of the ZrSi2 thin film as an EUV pellicle material was verified.
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