No abstract

No abstract

No abstract

No abstract

An average power tracking (APT) Doherty power amplifier (PA) is analyzed in terms of its biasing voltage condition, efficiency, and output power. And the drain and gate bias voltages are optimized for operation at different output power conditions. The Doherty power amplifier is designed using 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The bias voltages are controlled for each average power level(42.9 dBm, 39.9 dBm, 37 dBm). The measured drain efficiencies and gains are 53.2%, 12.8 dB at 42.9 dBm and 54.3%, 11.2 dB at 39.9 dBm and 53.4%, 9.1 dB at 37 dBm for a 10 MHz LTE signal with a 6.5 dB PAPR. This result demonstrates that the Doherty PA can be reconfigured for different average output powers using the bias voltage control method. Index Terms-Average power tracking (APT), Doherty power amplifier (DPA), drain efficiency (DE), Gallium nitride (GaN), long term evolution (LTE).

No abstract

No abstract

This article presents a cryo-CMOS quantum controller IC for superconducting qubits. The proposed globally synchronized clock system internally generates different local oscillator (LO) frequencies using multiple phase-locked loops (PLLs) driven by a common reference clock. It provides flexibility in spectral management as well as scalability for expansion to a large-scale quantum controller. The test chip includes two PLLs, four pulse modulator channels, and two receiver channels. Implemented chip in 40-nm CMOS shows full functionalities at 3.5 K. The designed pulse modulator circuits are verified with the specifications for expected fidelity of 99.99%.