We report the breakdown behavior of a patterned Ge2Sb2Te5 multiline structure during the voltage-driven electric stress biasing. Scanning Auger microscope analysis shows that the breakdown process accompanies with a phase separation of Ge2Sb2Te5 into an Sb, Te-rich phase and a Ge-rich phase. The phase separation is explained by the incongruent melting of Ge2Sb2Te5 based on the pseudobinary phase diagram between Sb2Te3 and GeTe. It is claimed that this phase separation behavior by incongruent melting provides one of the plausible mechanisms of the device failure in a phase change memory.
We report separate domain formation in cosputtered Ge2Sb2Te5–SiOx mixed layer, with SiOx amount less than 10mol%. As-prepared Ge2Sb2Te5–SiOx layer exhibits amorphous phase with separate domains smaller than 20nm. The separation maintains after thermal annealing, which results in crystallization into fcc phase. The crystallization activation energies of Ge2Sb2Te5–SiOx are obtained as 4.99 and 6.44eV for mixed layers containing 5.3 and 8.4mol% SiOx, respectively. Those are larger than 2.75eV of pure Ge2Sb2Te5. Furthermore, the mixed layer exhibits sublimation at increased temperature. These are interpreted as formation of Ge2Sb2Te5-rich domains separated from each other by SiOx-rich domains.
Amorphous Ge 2 Sb 2 Te 5 clusters with a size of 20 nm, self-enclosed by a thin layer of TiO x , were obtained by cosputtering Ge 2 Sb 2 Te 5 and TiO 2 targets at room temperature with the aim of reducing the reset current for phase change random access memory applications. Eutectic decomposition during the deposition caused a phase separation of Ge 2 Sb 2 Te 5 and TiO x . The temperature-dependent resistance change results showed that the activation energy for crystallization increased from 2.44 Ϯ 0.76 to 3.84 Ϯ 1.43 eV in the Ge 2 Sb 2 Te 5 film. The set resistance can be tuned within an acceptable range, and the reliability of this microstructure during repetitive laser melt-quenching cycles was tested.
Fluctuations (or drifts) in switching voltages such as programming set/reset voltages and threshold voltage pose serious obstacles to the reliable operation of electrical phase change memory devices. Using a phase change memory device having a GeSb2Te4 phase change material and TiN electrode, these fluctuations are demonstrated to result from device resistances varying with programming cycles. Fluctuating resistances appear to stem primarily from large contact resistances at the interface between the phase change material and the TiN electrode and from inhomogeneous phase distribution across the GeSb2Te4 layer due to unsuccessful heat confinement near the interface with TiN. Oxidation of a TiN electrode surface (via thermal annealing at 350°C under an atmospheric gas mixture of 97.9vol% N2 and 2.1vol% O2) is very effective in the reduction of fluctuations in device resistances and switching voltages hence the resulting increase in the programming cycles by two orders of magnitude. From a high resolution transmission electron microscopy, the oxidized surface was shown to consist of a titanium oxide layer primarily with Ti2O3 crystallites which is presumed to yield enhanced stability of the device by the following two effects. Firstly, Ge, Sb, and Te atoms would have stronger bonds to oxygen atoms than to nitrogen atoms by about 0.5eV, thereby producing more robust interface. Accordingly, the magnitude of contact resistance and its variation are reduced significantly so as to have little influence on the device resistances and their fluctuations. Secondly, thermally and electrically more resistive nature of the oxide layer would tend to yield, by enhanced generation and confinement of Joule heat, more uniform temperature distribution across the phase change material layer, rendering possibly a more homogeneous single phase material hence steadier sheet resistances with programming cycles.
Nanometer scale Ge2Sb2Te5 (GST) domains formed by immiscible mixture of GST-SiOx at room temperature and 180 °C show remarkable suppression in electrical and thermal conductivity. Thermal boundary resistance with increased GST-SiOx interface becomes crucial to the reduction in thermal conductivity. These conductivity reductions concurrently result in the reduction in programming current and power consumption in phase change memory devices.
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