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The feasibility of a neural network method was discussed in terms of a self-tuning proportional–integral–derivative (PID) controller. The proposed method was configured with two neural networks to dramatically reduce the number of tuning attempts with a practically achievable small amount of data acquisition. The first network identified the target system from response data, previous PID parameters, and response characteristics. The second network recommended PID parameters based on the results of the first network. The results showed that it could recommend PID parameters within 2 s of observing responses. When the number of trained data was as low as 1000, the performance efficiency of these methods was 92.9%, and the tuning was completed in an average of 2.94 attempts. Additionally, the robustness of these methods was determined by considering a system with noise or a situation when the target position was modified. These methods are also applicable for traditional PID controllers, thus enabling conservative industries to continue using PID controllers.

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For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

The retention of electrical performance under the combined conditions of mechanical strain and an electrical current is essential for flexible electronics. Here, we report that even below the critical current density required for electromigration, the electrical current can significantly deteriorate the electromechanical performance of metal film/polymer substrate systems. This leads to a loss of stretchability, and this effect becomes more severe with increasing strain as well as increasing current. The local increase of electrical resistance in the metal film caused by damage, such as localized deformations, cracks, etc., locally raises the temperature of the test sample via Joule heating. This weakens the deformation resistance of the polymer substrate, accelerating the necking instability, and consequently leading to a rapid loss of electrical conductivity with strain. To minimize such a current-induced deterioration of the polymer-supported metal films, we develop and demonstrate the feasibility of two methods that enhance the deformation resistance of the polymer substrate at elevated temperatures: increasing the thickness of the polymer substrate, and utilizing a polymer substrate with a high glass transition temperature.

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