Wafer level critical dimension control in spacer-defined double patterning for sub-72 nm pitch logic technologya)By the development of the double exposure technique or the double patterning technique, the pattern placement error of a photomask is interesting because of its impact on the size and position of wafer pattern. Among various sources to induce the pattern placement error, we have focused on the charging effect of the FEP-171 resist and have shown that the resist charging effect generates the pattern position error of a clear pattern and the critical dimension variation of a dark pattern. Based on experiment and simulation, we present quantitatively the dependence of position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe the charging effect and its agreement with experiment and the correction method to remove the resist charging effect.