In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding Compound (EMC) selection approach, air vent design of cavity vacuum molding, and void formation mechanism by mold flow simulation and DOE(Design of Experiment) of several SIP module layouts. The test vehicle used for this study of MUF by vacuum transfer molding shown as SiP module (8.2×7.7×1.13mm) which was sawn from 52.70×68.70×0.75mm mold area of 118.5*75.5*0.38 substrate. One segment mold inside (52.70× 68.70×0.75mm) had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51×5.81×0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705×0.705× 0.33mm) which had 4 bumps and 85um bump height, 1.6×0.8×0.6mm size of LC filter, and total 25ea passives. In the end, SAT result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.
Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.
In this study, we developed the molded underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated sideby-side. This study covered not only MUF reliability performance but also MUF design study focused on minimizing voids between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding compound (EMC) selection approach, air vent design of cavity vacuum molding, and results of void free from Design of Experiment (DOE) of several SiP module layouts. In the end, Scanning Acoustic Tomography (SAT) result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.
In this study, to increase solder joint reliability, we developed the epoxy reinforced bump structure surrounding the solder bump joint. The thermal-mechanical reliability of the epoxy reinforced solder bumped wafer level package was carried out during the thermal cycle and drop shock test of the package. The reliability of solder bump joint was evaluated by means of the thermal cycle in the range -40° to 125°. The experimental results revealed that the thermo-mechanical fatigue properties of the epoxy reinforced bump structure was better than that of the conventional solder bump structure. Epoxy reinforced bump structures improved the WLP characteristic life by at least 2 times. Also, the drop shock reliability of epoxy reinforced bump structure was enhanced 3 times better drop characteristic life than that of conventional single bump structure. The life time of epoxy reinforced solder bump joint was longer than that of the conventional WLCSP solder joint.
Recently, there are increasing demands of a size reduction and a fine interconnection technology, especially for System-in-Package (SiP) module and Package on Package (POP) module in a smart phone and a wearable electronic device. In this study, we presented the Plating Mold Via (PMV) interconnection technology as an innovative fine pitch interconnection solution between substrate I/O pads and package I/O pads in molded System-in-Package (SiP) modules. Similar to the Through Mold Via (TMV), the laser mold via process is first performed to produce a through-via in the Epoxy Mold Compound (EMC) mold, but plating and Soldering process are used simultaneously to produce the metallurgical interconnection to embody the I/O pins of the over-molded surface. After the PMV technology is described, a study of PMV in the molded packaging module is followed. The study is conducted using a test vehicle of SiP module that contains flip chips, Quad Flat Non-leaded (QFN) packages and passives. It is focused on several interface reliability issues, including the interfacial strength of PMV to substrate metal pad as well as to the laser projected area of EMC, and the study of IMC at the plating metal and solder interfaces. The study clearly shows that the PMV technology is a promising fine pitch interconnect solution for various SiP modules.
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