Resist reflow is a simple and cost-effective technique of fabricating a sub-100 nm contact hole (CH) pattern. The predominant factors affecting resist reflow include baking temperature and time, the volume surrounding the CH, the pattern layout, and the resist material properties. Thus, to optimize the layout design and process parameters, we developed a simple resist flow model that could predict the resist reflow tendency as functions of the reflow temperature, CH size, and the initial shape, the pitch and irregularity of CH array. The basic fluid equation was used to express the flow of the resist, and the variations of viscosity and density as functions of reflow temperature and time were considered. We also included the surface tension and bulk effect in our reflow model, so that we could see the difference in CH surface roundness with different surface tensions. We could also see the difference in CH size among the irregular CHs and those with different duty ratios by including the bulk effect. Moreover, we simply attempted to correct the critical dimension difference with pitch as imposing a bias on each afterdevelopment contact hole.
Abstract-WLP (Wafer level packaging) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to establish electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and TSV (Through Silicon Via). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Key fabrication processes include glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is needed for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.
When a picture contains non-translational motions in it, a picture-level parametric motion model can be more efficient than the block-based translational motion model because the former has small number of parameters that can replace many motion vectors of individual blocks. In addition, the former can represent the deformation of the image better than the latter. Based on this idea, we detected multiple homography transformations between a reference and a current picture. Then, we generated warped reference pictures 1 corresponding to the homographies and inserted the one of the warped reference pictures into reference picture lists.We measured the performance of the proposed algorithm using the test condition that is proposed by MPEG and ITU recently. Experimental result showed 3.1% overall bitrate saving under low delay & high efficiency condition and 3.5% overall bitrate saving under random access & high efficiency condition compared with TMuC 0.7.3.
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