PANEL SUMMARYThermal issues are becoming more important but is the hype getting the better of the facts? Does this deserve more attention than for some niche designs and technologies such as 3D ICs.? Does the broader design community need to worry about it at 32nm and beyond or it will only impact a small segment of designs? In short, does the severity of power issues coupled with packaging complexity translate into a thermal crisis in future? This is an educational panel with a little bit of controversy that will address the thermal issue in IC design. When will this issue be emerging as a crucial concern if at all? What are the solutions to resolve this potential crisis? PANELIST VIEWPOINTSDarvin Edwards: Thermal issues are becoming a larger design concern across all manner of devices and systems. High performance microprocessors are pushing the limits of air cooling with growing die sizes, growing parasitic leakage powers, and higher powers in general, though several design, process and software tricks are being used to slow the growing power dissipation trend. On the low end, DC-to-DC converts and digital amplifiers are becoming ever smaller and more efficient, but are experiencing higher power densities per mm 2 which must be cooled. New classes of packages including stacked die packages and package-on-package (POP) have led to higher power densities on the PCB, creating PCB hot spots which must be managed. Other packaging technologies on the horizon such as embedded die and 3D through-silicon via technology (TSV) promise to make this situation worse. System on a chip (SOC) solutions often integrate logic, memory, and driver type devices which can result in high thermal gradients on the die, as can high current transistors on analog devices. These on die hot spots can no longer be ignored, but must be managed in the design phase. Existing tools to co-design thermal performance and die layouts are sub-optimal for the task. Future process roadmaps show reduced maximum junction temperatures for some logic devices which will only make thermal management more difficult.Several other trends are driving thermal management complexity. Incremental battery capacity improvements allow higher portable power dissipation for functions such as games and video, while the drive towards more compact circuit subsystems results in higher power densities and potentially more thermal problems. A series of recent product thermal issues reported in trade journals highlight the failure of many design engineers to appropriately account for these challenges. As well, the limits of available power generation infrastructure to supply and cool the plethora of new electronic products are causing a growing level of legislative initiatives to dictate power dissipation performance per function.This confluence of factors is driving the need for more thermal engineers to perform better system level analysis, better thermal modeling tools which are more flexible, faster and detailed, and a higher level of accuracy in IC package abstraction (com...
The demand for high speed, low power and low cost for Viterbi decoding especially in wireless communication are always required. Thus this paper presents the design of an adaptive Viterbi decoder that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase the speed. Viterbi Algorithm is the optimum-decoding algorithm for convolutional codes and has often been served as a standard technique in digital communication systems for maximum likelihood sequence estimation. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. In this paper register exchange based survivor unit is used as they have better throughput when compared to trace back using memory. Branch metric is calculated for either upper or lower half of trellis, which leads to reduction of power consumption. The Trellis code structure is divided into two segments. The first segment of the Trellis works in normal Viterbi mode while the second works in modified T-algorithm. The designed Adaptive Viterbi Decoder is able to detect and correct up to four errors. The design is optimized with respect to time, area and power and the netlist is generated. The netlist obtained after synthesis undergoes the physical design process. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx FPGA device.
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