Keeping hot chips cool

Abstract

PANEL SUMMARYThermal issues are becoming more important but is the hype getting the better of the facts? Does this deserve more attention than for some niche designs and technologies such as 3D ICs.? Does the broader design community need to worry about it at 32nm and beyond or it will only impact a small segment of designs? In short, does the severity of power issues coupled with packaging complexity translate into a thermal crisis in future? This is an educational panel with a little bit of controversy that will address the thermal issue in IC design. When will this issue be emerging as a crucial concern if at all? What are the solutions to resolve this potential crisis? PANELIST VIEWPOINTSDarvin Edwards: Thermal issues are becoming a larger design concern across all manner of devices and systems. High performance microprocessors are pushing the limits of air cooling with growing die sizes, growing parasitic leakage powers, and higher powers in general, though several design, process and software tricks are being used to slow the growing power dissipation trend. On the low end, DC-to-DC converts and digital amplifiers are becoming ever smaller and more efficient, but are experiencing higher power densities per mm 2 which must be cooled. New classes of packages including stacked die packages and package-on-package (POP) have led to higher power densities on the PCB, creating PCB hot spots which must be managed. Other packaging technologies on the horizon such as embedded die and 3D through-silicon via technology (TSV) promise to make this situation worse. System on a chip (SOC) solutions often integrate logic, memory, and driver type devices which can result in high thermal gradients on the die, as can high current transistors on analog devices. These on die hot spots can no longer be ignored, but must be managed in the design phase. Existing tools to co-design thermal performance and die layouts are sub-optimal for the task. Future process roadmaps show reduced maximum junction temperatures for some logic devices which will only make thermal management more difficult.Several other trends are driving thermal management complexity. Incremental battery capacity improvements allow higher portable power dissipation for functions such as games and video, while the drive towards more compact circuit subsystems results in higher power densities and potentially more thermal problems. A series of recent product thermal issues reported in trade journals highlight the failure of many design engineers to appropriately account for these challenges. As well, the limits of available power generation infrastructure to supply and cool the plethora of new electronic products are causing a growing level of legislative initiatives to dictate power dissipation performance per function.This confluence of factors is driving the need for more thermal engineers to perform better system level analysis, better thermal modeling tools which are more flexible, faster and detailed, and a higher level of accuracy in IC package abstraction (com...

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

“…3 shows a simple schematic of a logic block that has been power gated by a header switch or a footer switch. While the logic block is not active, assertion of the SLEEP signal results in turning off the either of the switches, thus disconnecting the logic block from supply, and reducing the leakage by orders of magnitude [24]. This technique is widely applied for implementing various sleep modes in CPUs.…”

Design Aid of Multi-core Embedded Systems with Energy Model

“…As technology advances static power increases more rapidly than dynamic power [1], and now it gets comparable to dynamic power consumption. As static power is consumed without any contribution to computing, its reduction is strongly required.…”

“…As static power is consumed without any contribution to computing, its reduction is strongly required. A wide variety of power reduction techniques has been proposed and realized, including clock gating, power gating, DVFS, and so 1 The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan 2 Renesas Electronics Corporation, Chiyoda, Tokyo 100-0004, Japan †1…”

Low power clock buffer planning methodology in F-D placement for large scale circuit design

“…To alleviate power consumption, a latch clumping technique considering buffer and latch placement is proposed in [7]. It is based on the observation that most of power is dissipated in the lower level subtrees which are driven by low level clock buffers that directly drive the latches.…”