The exotic electrodynamics properties of graphene come from the linearly dispersive electronic bands that host massless Dirac electrons. A similar behavior was predicted to manifest in freestanding silicene, the silicon counterpart of graphene, thereby envisaging a new route for a silicon photonics. However, the access to silicene exploitation in photonics was hindered so far by the use of optically inappropriate substrates in experimentally realized silicene. Here we report on the optical conductivity of silicon nanosheets epitaxially grown on the optically transparent Al2O3(0001) from a thickness of a few tens of nanometers down to the extreme twodimensional (2D) limit. When approaching a 2D regime, a Dirac-like electrodynamics can be deduced from the observation of a low-energy optical conductivity feature owing to a silicene-based interfacing to the substrate.
Ge-rich GST alloys are the most promising materials for phase-change memory (PCM) to fulfill the soldering compliance and the tough data retention requirements of automotive applications. Significant efforts have been made to engineer those materials and optimize their integration inside the fabrication process of PCM. In this perspective, the physical characterization of the device and the material is instrumental in understanding the underlying physics, improving the process, and optimizing the interactions between the device, the process, and the material itself. Especially, microscopic investigations have gathered increasing interest, giving detailed descriptions of local material modulations that have a crucial role in cell programming and reliability performances. In this work, a deep analysis of Ge-rich GST microscopic alloy evolution during the integration process has been performed, exploiting analysis by EELS with TEM supported by a novel statistical data post-processing method. The new proposed statistical-based methodology also introduces new simple metrics for elemental compositional evaluations that have been exploited for process engineering.
The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.
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