Myriad 2 is a multicore always-on System-on-Chip supporting computational imaging and visual awareness for mobile, wearable, and embedded applications. The Myriad 2 VisionProcessing Unit (VPU) is based on the 128-bit SHAVE vector-processor and hardware acceleration pipeline backed by shared multicore memory subsystem and peripherals, and occupies 27mm 2 in 28nm HPM-CMOS. The device has been designed to operate at 0.9V for nominal 600MHz operation, and contains 17 different power-islands coupled with extensive clock-gating under a software API to minimise power-dissipation. The 12 integrated SHAVE processors combined with video hardware accelerators achieve 1000 GFLOPS (fp16 type) at 600mW including peripherals and stacked 32-bit wide 128MB LP DDR2 DRAM operating at 533MHz. The VPU incorporates parallelism, ISA and microarchitectural features such as multi-ported register-files and hardware support for sparse data-structures, video hardware accelerators, configurable multicore and multiported memory banks; thus it provides exceptional and highly sustainable performance efficiency across a range of computational imaging and computer vision applications including those with low latency requirements on the order of milliseconds.
Abstract:Myriad 2 is a multicore always-on System-on-Chip supporting computational imaging and visual awareness for mobile, wearable, and embedded applications. The Myriad 2 Vision Processing Unit (VPU) is based on the 128-bit SHAVE vector-processor and hardware acceleration pipeline backed by shared multicore memory subsystem and peripherals, and occupies 27mm 2 in 28nm HPM-CMOS. The device has been designed to operate at 0.9V for nominal 600MHz operation, and contains 17 different power-islands coupled with extensive clock-gating under a software API to minimise power-dissipation. The 12 integrated SHAVE processors combined with video hardware accelerators achieve 1000 GFLOPS (fp16 type) at 600mW including peripherals and stacked 32-bit wide 128MB LP DDR2 DRAM operating at 533MHz. The VPU incorporates parallelism, ISA and microarchitectural features such as multi-ported register-files and hardware support for sparse data-structures, video hardware accelerators, configurable multicore and multiported memory banks; thus it provides exceptional and highly sustainable performance efficiency across a range of computational imaging and computer vision applications including those with low latency requirements on the order of milliseconds.
The lost-in-space star identification algorithm is able to identify stars without a priori attitude information and is arguably the most critical component of a star sensor system. In this paper, the 2009 survey by Spratling and Mortari is extended and recent lost-in-space star identification algorithms are surveyed. The covered literature is a qualitative representation of the current research in the field. A taxonomy of these algorithms based on their feature extraction method is defined. Furthermore, we show that in current literature the comparison of these algorithms can produce inconsistent conclusions. In order to mitigate these inconsistencies, this paper lists the considerations related to the relative performance evaluation of these algorithms using simulation.
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