Myriad 2: Eye of the computational vision storm

Moloney, David; Cael, B. B.; Richmond, Richard D.; Connor, Fergal; Brick, Cormac; Donohoe, David

doi:10.1109/hotchips.2014.7478823

Cited by 28 publications

(20 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In this work, we have provided an overview of the Vision Processing Unit (VPU) as co-processor for inference on HPC. In particular, we have explored the most relevant technical details of the Myriad 2 VPU [13,14], in the context of the Intel Neural Compute Stick (NCS) platform [16]. To support our experiments, we have also presented a small inference framework, named…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Exploring the Vision Processing Unit as Co-Processor for Inference

Rivas-Gomez

Peña²,

Moloney

et al. 2018

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

View full text Add to dashboard Cite

The success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W.We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multi-VPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8× in comparison.

show abstract

Section: Resultsmentioning

confidence: 99%

“…The Myriad 2 VPU is designed as a 28-nm coprocessor that provides high-performance tensor acceleration. The chip dissipates less than 1W [13].…”

Section: Vision Processing Unitmentioning

confidence: 99%

Exploring the Vision Processing Unit as Co-Processor for Inference

Rivas-Gomez

Peña²,

Moloney

et al. 2018

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

View full text Add to dashboard Cite

show abstract

“…To support the understanding of our performance evaluation (Section 5), we outline the performance critical aspects of the design: 2. Each UAP lane is associated with one bank of an on-chip local memory [57,58] that provides fast access for transition primitives and actions (32 bits each). With a 16KB local memory bank, each UAP lane runs at 1.2GHz.…”

Section: Uap Architecturementioning

confidence: 99%

Fast support for unstructured data processing

You

Hoang

Becchi

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

View full text Add to dashboard Cite

We propose the Unified Automata Processor (UAP), a new architecture that provides general and efficient support for finite automata (FA). The UAP supports a wide range of existing finite automata models (DFAs, NFAs, A-DFAs, JFAs, counting-DFAs, and countingNFAs), and future novel FA models. Evaluation on realistic workloads shows that UAP implements all models efficiently, achieving line rates 94.5% of ideal. A single UAP lane delivers line rates 50x greater than software approaches on CPUs and GPUs. Scaling UAP to 64 lanes achieves FA transition throughputs as high as 295 Gbps, more than 100x higher than CPUs and GPUs, and even exceeding ASIC approaches such as IBM's RegX by 6x. With efficient support for multiple input streams, UAP achieves throughputs that saturate even high speed stacked DRAM memory systems.The UAP design and implementation is efficient in instructions executed, memory references, and energy. UAP achieves a 1.2 Ghz clock rate (32nm TSMC CMOS), and a 64-lane UAP requires only 2.2 mm 2 and 563 mW. At these levels of performance and energy-efficiency, UAP is a promising candidate for integration into generalpurpose computing architectures.

show abstract

“…Figure 2, based on [48,49], shows the architectural layout of a Myriad 2 Platform developed by Movidius Ltd [20]. It is an MPSoC containing multiple heterogeneous processors, hardware accelerators, memories, and external interfaces.…”

Section: Myriad 2 Architecturementioning

confidence: 99%

“…Myriad 2 contains 12 streaming hybrid architecture vector engine (SHAVE) and two reduced instruction set computing (RISC) processors. SHAVE processors are the real workhorse of Myriad 2 and are designed to crunch the complex imaging and vision algorithms [48]. The platform offers a 2 MB connection matrix (CMX) memory along with a number of programmable hardware accelerators for vision processing.…”

Section: Myriad 2 Architecturementioning

confidence: 99%

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Mustafa

O’Riordan

Rogers

et al. 2018

J Real-Time Image Proc

View full text Add to dashboard Cite

Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls (MBS) making a significant part of their execution time. For maximum reduction in memory stalls, compilers need to consider architectural details of a platform and utilize its hardware components efficiently. In this paper, we propose a compiler optimization for a vision-processing system through classification of memory references to reduce MBS. As the proposed optimization is based on the architectural features of a specific platform, i.e., Myriad 2, it can only be applied to other platforms having similar architectural features. The optimization consists of two steps: affinity analysis and affinity-aware instruction scheduling. We suggest two different approaches for affinity analysis, i.e., source code annotation and automated analysis. We use LLVM compiler infrastructure for implementation of the proposed optimization. Application of annotation-based approach on a memory-intensive program shows a reduction in stall cycles by 67.44%, leading to 25.61% improvement in execution time. We use 11 different image-processing benchmarks for evaluation of automated analysis approach. Experimental results show that classification of memory references reduces stall cycles, on average, by 69.83%. As all benchmarks are both compute and memory intensive, we achieve improvement in execution time by up to 30%, with a modest average of 5.79%.

show abstract

Myriad 2: Eye of the computational vision storm

Cited by 28 publications

References 0 publications

Exploring the Vision Processing Unit as Co-Processor for Inference

Exploring the Vision Processing Unit as Co-Processor for Inference

Fast support for unstructured data processing

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Contact Info

Product

Resources

About