Wet processes using organic solvents are gaining a renewed interest for stripping high dose ͑ м 1 ϫ 10 15 atoms . cm −2 ͒ ionimplanted photoresist ͑II-PR͒ in front-end-of-line semiconductor manufacturing because of their excellent selectivity to ultrashallow implanted substrates and novel materials. However, the highly cross-linked resist layer ͑so-called crust͒, formed on the top and sidewalls of the resist has very limited solubility in organic solvents unlike the underlying nonimplanted resist ͑bulk͒. This study investigates the effect of UV pre-and post-treatment on II-PR for enabling its removal by organic solvent. Moreover, the impact of the UV wavelength, dose, and power density on the crust and bulk is presented. Optimal conditions of the UV pre-and post-treatment can be determined. Short ͑ Ͻ 200 nm͒ and long wavelengths ͑300-400 nm͒ at low doses induce more scission of the crust with less cross-linking of the bulk, resulting in higher solubility of the II-PR in organic solvents. Moreover, the short wavelength pretreatment is advised because of its bigger effect on the crust, resulting in significant enhancement of the residue removal. In addition, a post-treatment using short wavelengths has high removal efficiency in contrast to the long wavelengths treatment. Finally, no significant impact of the power density is revealed.
Removal of SiARC containing photo resist stacks presents significant challenges to conventional plasma dry strip tools. Due to the high Si content (35-45% Si), the SiARC removal process must typically be done with a combination of dry and wet processes or done entirely in an etcher. As both the Dry-Wet-Dry and the Etcher approach to SiARC stack removal are long and high cost processes, a single chamber, dry-only solution to SiARC stack removal is highly desirable. This paper reports the dry strip process developed at Axcelis Technologies, Inc. to remove the SiARC stack layer by layer which results in a residue free oxide substrate.
The removal of ion implanted photoresist (II-PR) after implantation of ultra shallow extension and halo regions is considered as one of the most challenging front-end-of-line (FEOL) processing steps for 32nm and beyond CMOS technology nodes. Commonly used resist strip processes such as fluorine-based dry plasma ash and hot sulfuric/peroxide mixtures induce unacceptable levels of oxidation and material loss [1-.
Nicholas.CIements@,infineon.com P a u l . J o w e t t @ l &hen.F ereusonlhinfineon. c o q pan.Manson@infineon.co m Cort.Dem-' MarkRichmo
AbstractSignficanrfinancial benefifs are realized by reducing the wafer edge erclurion to gain additional producfive chips as well as enhance the yield of fhe former edge-mosr region of the wafer. Challenges are discussed and cos:. ejfpcrive solutions provided for major unir process and inlegration issues such as plasma-efch induced blocked/dis:ortedpa:tern, image displacement, inrerlayer misalignment, lifhography edge coating and pafterning, pafterndensifydependenf CMP and Etch nonuniformify, scribe readability. and shared-driver shorfs.
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