Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

Negative resistance behavior and reproducible resistance switching were found in polycrystalline NiO films deposited by dc magnetron reactive sputtering methods. Oxygen to argon gas ratio during deposition was critical in deciding the detailed switching characteristics of either bi-stable memory switching or mono-stable threshold switching. Both metallic nickel defects and nickel vacancies influenced the negative resistance and the switching characteristics. We obtained a distribution of low resistance values which were dependent on the compliance current of high-to-low resistance switching. At 200°C, the low-resistance state kept its initial resistance value while the high-resistance state reached 85% of its initial resistance value after 5×105s. We suggested that the negative resistance and the switching mechanism could be described by electron conduction related to metallic nickel defect states existing in deep levels and by small-polaron hole hopping conduction.

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.

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Nowadays flash memory is one of the most frequently used nonvolatile memories in electronic devices. However, since flash memory is based on Si transistors with floating gates which can store electronic charges, it has basic limitations in its speed and density. It takes longer than 1 lsec for electronic charges to be stored in a floating gate in one cell of flash memory. In addition, we'll reach density limitation in flash memory in the near future by conventional scaling methods, such as decrease in gate length or increase in dielectric constant of the gate oxide, which are commonly applied to Sibased 2-dimensional devices. Thus, in order to overcome the limitations of flash memory, we require a new nonvolatile memory which is not based on Si devices with electronic charge storing phenomena. Here we introduce a next generation nonvolatile memory consisting of two oxide resistors, NiO and VO 2 , where the former is a memory element storing data by utilizing so called bi-stable resistance switching and the latter is a switch element controlling access using the related threshold switching. Since the memory only utilizes resistance switching behaviors of the two oxide resistors, writing and reading times are around several 10s of ns. In addition, it overcomes density limitations by its compatibility with 3-dimensional stack structures due to its low processing temperature lower than 300°C. High performance tests show the feasibility of a universal memory which has advantages of both flash and static random access memories.Si-based flash memory has become the standard for nonvolatile memory which does not lose information in the absence of an external bias. Nonetheless it faces several barriers as cell size is reduced beyond the sub-micrometer region (currently having realized a 40 nm pattern for 32 gigabit NAND flash memory) [1] due to charge leakage across the tunnel oxide. In addition, it needs a little longer time (> 1 ls) to write information by storing charges in a floating gate of flash memory. The efforts of the semiconductor industries have been focused not only on developing scaling methods or modifying device structures for Si-based flash memories [1] but on finding a next generation memory using materials which can circumvent the fundamental limits of Si. The goal of a next generation memory is both to surpass flash memory for nonvolatile memory applications and to realize a universal memory which combines the advantages of nonvolatile slow memory such as flash memory and volatile fast memory such as static random access memory. In order to accomplish this, a class of materials and structures which have easy scalability and rapid programming speed in addition to nonvolatility and low power consumption must be developed. In general, nonvolatile memory consists of a memory element with bi-stable states under zero bias and a switch element with resistance controlled by external bias. The memory element stores the information and the switch element controls access to a specific memory element. Several gro...

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT.

A one-bit cell of a general nonvolatile memory consists of a memory element and a switch element. Several memory elements have been tried given that any bistable states, that is, two charging states, two spin states, or two resistance states, can be used for a memory element. On the other hand, silicon-based transistors have been the most popularly used switch element. However, silicon-based transistors do not conform to high-density, nonvolatile memories with three-dimensional (3D) stack structures due to their high processing temperatures and the difficulty of growing high-quality epitaxial silicon over metals. Here, we show a low-temperaturegrown oxide diode, Pt/p-NiO x /n-TiO x /Pt, applied as a switch element for high-density, nonvolatile memories. The diode exhibits good rectifying characteristics at room temperature: a rectifying ratio of 10 5 at ± 3 V, a forward current density of up to ∼ 5×10 3 A cm -2 , an ideality factor of 4.3, and a turn-on voltage of 2 V. Furthermore, we verify its ability to allow and deny access to the Pt/NiO/Pt memory element with two stable resistance states. Under the forward-bias condition, we could access the memory element and change the resistance state, although access was denied under the reverse bias condition. This one-diode/one-resistor (1D/1R) structure could be a promising building block for high-density, nonvolatile random-access memories with 3D stack structures.