A technique for optimizing the number of channels for time-interleaved sample-and-hold is proposed. This technique permits to extract the figure of merit of a single sampleand-hold circuit while taking into account the limited gainbandwidth of a family of operational amplifiers sharing the same topology. A double-sampled architecture of sample-and-holds is used to reduce die area and power consumption. The extracted results allow us to determine the optimal operation frequency and consequently the optimal number of channels for a given sampling frequency required by the time-interleaved sample-andhold. A demonstration is shown for a gain boosted folded cascode operational amplifier topology in a 65 nm technology.
This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal and, on the other hand, a new blind clock skew detection algorithm that guides the adaptive filters. This calibration method applies to any number of parallel channels in a time-interleaved architecture. Here we show theoretical analysis and simulation results for 4 channels case. It is concluded that the calibration technique can greatly attenuate the spurs and improve the SNDR.
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