Optimizing the number of channels for time interleaved sample-and-hold circuits

Jabbour, Chadi; Camarero, David; Nguyen, Van Tam; Loumeau, Patrick

doi:10.1109/newcas.2008.4606367

Cited by 6 publications

(5 citation statements)

References 15 publications

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“…On each clock cycle, one ADC goes from track to hold, capturing a sample of the input signal. The disadvantage of this structure is that the input capacitance of the TI‐ADC becomes very large, which limits the system bandwidth [19]. The second type is S&H with a front‐end sampler.…”

Section: Sandh Circuitmentioning

confidence: 99%

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

Siddiqui

Choi

2020

IET Circuits, Devices & Systems

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The performance of a wideband receiver is highly dependent on the performance of the analogue-to-digital converter (ADC) used. Such applications require ADCs to operate at ultra-high speeds with high accuracy for inputs ranging from 40 MHz-1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low-speed ADC or use a single ultra-high-speed flash converter. Both of these solutions consume ultra-high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time-interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy-saving capabilities of a time-interleaving structure, the circuit adopts amplifier sharing in sample-and-hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal-to-noise-and-distortion ratio of 53.65 dB and spurious-free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure-of-merit of 0.67 pJ/conv-step.

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Section: Sandh Circuitmentioning

confidence: 99%

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

Siddiqui

Choi

2020

IET Circuits, Devices & Systems

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“…13 points spectrum requires a simulation of 2 13 9 N cycles of the complete circuit which requires a very long simulation time. Therefore, for the UMTS/DVBT scenario, the output SNDR was estimated based on the results of electrical simulations of one channel and the results of system level simulations This represents only a 15% die increase and a 10% power consumption increase compared to the interpolation network required for the classical technique.…”

Section: Interpolation Network Implementationmentioning

confidence: 99%

“…The major benefit of all of these approaches is that they increase the conversion bandwidth with a linear increase of the power consumption whereas with a single sigma-delta modulator, the power consumption increases exponentially while drastically increasing the bandwidth [13].…”

Section: Introductionmentioning

confidence: 99%

A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters

Beydoun

Jabbour

Nguyen

et al. 2011

Analog Integr Circ Sig Process

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Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65 nm CMOS process.

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“…The major benefit of the EFBD architecture is that it allows to increase the conversion bandwidth with a linear increase of the power consumption (the total power consumption is N +2 times the power consumption of one modulator) whereas with a single bandpass sigma-delta modulator, the power consumption increases exponentially while increasing the bandwidth [13].…”

Section: Theorymentioning

confidence: 99%

Extended frequency-band-decomposition sigma–delta A/D converter

Bénabès

Beydoun

Oksman

2009

Analog Integr Circ Sig Process

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Frequency-Band-Decomposition (FBD) is a good candidate to be used to increase the bandwidths of ADC converters based on sigma-delta modulators for software and cognitive radio applications where we need to convert wide bandwidths. Each modulator processes a part of the band of the input signal which is then passed through a digital filter. In the case of large mismatches in the analog modulators, a new solution, called Extended Frequency-Band-Decomposition (EFBD) can be used. As an example, this solution can allow for a 4 % error in the central frequencies without significant degradation of its performance when the digital processing part is paired with the analog modulators. A calibration of the digital part is thus required to reach these theoretical performances. This paper will focus on a self-calibration algorithm for an EFBD. The algorithm helps minimize the quantization noise of the EFBD and helps to flatten the signal transfer function.

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Optimizing the number of channels for time interleaved sample-and-hold circuits

Cited by 6 publications

References 15 publications

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters

Extended frequency-band-decomposition sigma–delta A/D converter

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