With each new technology node, there is as usual a corresponding tightening of the overlay requirements. To achieve these requirements in production there is increasingly a need to apply APC strategies, in order to control overlay. However, in order to control overlay successfully using such APC strategies, it is critical to have a thorough understanding of all the sources of overlay error, both grid and intrafield, that contribute to the total overlay budget. Without this thorough understanding, it becomes difficult to establish whether the APC strategy is actually reducing the sources of overlay variation, or in the worst case, actually responsible for their increase.In this paper we present an analysis of the sources of overlay error for three ASML step and scan tools, rank their relative significance and develop a methodology for controlling them by means of an APC strategy. The analysis is based on data collected over a period of more than four months using a baseline monitor. Stability is monitored both with and without feedback corrections from an APC system, in order to optimize the APC strategy. From the analysis we propose a knowledge based APC methodology, using feedback optimization, for overlay control of ASML step and scan exposure tools.
Overlay lot disposition algorithms in lithography occupy some of the highest leverage decision points in the microelectronic manufacturing process. In a typical large volume sub-0. 1 8m fab the lithography lot disposition decision is made about 500 times per day. Each decision will send a lot of wafers either to the next irreversible process step or back to rework in an attempt to improve unacceptable overlay performance. In the case of rework, the intention is that the reworked lot will represent better yield (and thus more value) than the original lot and that the enhanced lot value will exceed the cost of rework. Given that the estimated cost of reworking a critical-level lot is around $ 10,000 (based upon the opportunity cost of consuming time on a state-of-the-art DUV scanner), we are faced with the implication that the lithography lot disposition decision process impacts up to $5 million per day in decisions. That means that a 1 % error rate in this decision process represents over $ 1 8 million per year in lost profit for a representative site.Remarkably, despite this huge leverage, the lithography lot disposition decision algorithm usually receives minimal attention. In many cases, this lack of attention has resulted in the retention of sub-optimal algorithms from earlier process generations and a significant negative impact on the economic output of many high-volume manufacturing sites. An ideal lot-dispositioning algorithm would be an algorithm that results into the best economic decision being made every time -lots would only be reworked where the expected value (EV) of the reworked lot minus the expected value of the original lot exceeds the cost of the rework: EV(reworked lot) -EV(original lot) > COST(rework process)Calculating the above expected values in real-time has generally been deemed too complicated and maintenance-intensive to be practical for fab operations, so a simplified rule is typically used. PROJECTED MAXIMUM ERROR > ESTIMATED YIELD LOSS THRESHHOLDSuccessful implementation of the Projected Maximum Error rule in lieu of the more complex Expected Value rule relies on two things -an accurate estimate of the yield loss threshold and an accurate method for calculating the projected maximum error. In this paper we performed an exhaustive comparison between 3 different methods for calculating the projected maximum error.
Driven by overlay shrinks and increasing product diversification in advanced fabs, automatic control of correctable overlay coefficients has become critical to semiconductor manufacturing. Although numerous reports have shown the compelling benefits of automatic run-to-run feedback control, one important issue has received very little attention to date. In many state-of-the-art fabs, reticle to wafer alignment is performed against marks that were printed at the firstor zero-level, whereas overlay is still measured between a target level and one or two reference levels. In many cases, perturbations of the reference level are unknown at the time of target level exposure.In this study, we will show how the perturbations of the reference level can impact overlay controllability at cascading levels (levels where overlay is measured against the reference level, but exposure tool alignment is done to the zero level). We will also show that once the perturbation is understood, it can be accounted for at the time of exposure, thus presenting an opportunity for additional overlay improvement.
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