The focus of this work is to perform the experimental comparative study between Diamond and the conventional MOSFET counterpart in order to verify the benefits observed by three dimensional numerical simulations, considering the same geometric factor, die area and bias conditions, as described in first publication of Diamond style layout. The devices were manufactured by using the commercial manufacture CMOS process from 0.35μm AMI (On-Semiconductor) that is available in MOSIS Educational Program (MEP). The experimental results prove that Diamond MOSFET presents a better performance than one found in equivalent conventional transistor, except in relation to the Early voltage, due the higher impact ionization in the drain region than one observed in the conventional counterpart. Therefore the Diamond layout style is an important alternative to improve the performance of the analog, current drivers and pass switches integrated circuits applications.
This work introduces and studies a new transistor layout style, called Fish SOI MOSFET using 3D numerical simulations, where two trapezes compose the transistor gate area, generating a "smaller than (<)" mathematical signal shape. This innovative layout structure is an evolution of the Diamond SOI MOSFET. The Fish structure was carefully designed to be used in the digital integrated circuits applications, because now its channel length can be implemented with the minimum dimension allowed by the manufacture process, in contrast to Diamond transistor in which this is not possible. The Fish transistor also uses the Longitudinal Corner Effect (LCE) to increase the resultant longitudinal electric field along to the channel length, that results in an improvement in the average carriers drift velocity in the channel, in the drain current, in the transconductance and in the on-state series resistance parameters.
This paper is conceptual and introduces a new transistor layout style called FISH SOI MOSFET (FSM). It is an evolution of the Diamond device (DSM) and specially designed to preserve the Longitudinal Corner Effect (LCE) to increase the resultant longitudinal electric field along the channel, that results in an improvement in the average carrier drift velocity in the channel. It presents a gate geometric shape similar to a "smaller than (<)" mathematical symbol. Unlike the DSM, the FISH layout style brings an innovative possibility in the lengthening of its effective channel length, defined as "Lengthening of Effective Channel Length Effect (LECLE)," keeping the channel length with the minimum dimension allowed by the SOI CMOS process technology used in manufacturing digital ICs applications. It can reduce the die area of digital ICs by using the LECLE of the FISH layout structure style by combining conventional SOI pMOSFETs and FISH nMOSFETs. Thanks to the FSM LECLE, one also can reduce the die area of the current mirrors of analog integrated circuits. For the first time, it is shown that LECLE in the FSM structure is able to increase the Early voltage and consequently to improve significantly the voltage gain of analog ICs.
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