FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications

Abstract

This work introduces and studies a new transistor layout style, called Fish SOI MOSFET using 3D numerical simulations, where two trapezes compose the transistor gate area, generating a "smaller than (<)" mathematical signal shape. This innovative layout structure is an evolution of the Diamond SOI MOSFET. The Fish structure was carefully designed to be used in the digital integrated circuits applications, because now its channel length can be implemented with the minimum dimension allowed by the manufacture process, in contrast to Diamond transistor in which this is not possible. The Fish transistor also uses the Longitudinal Corner Effect (LCE) to increase the resultant longitudinal electric field along to the channel length, that results in an improvement in the average carriers drift velocity in the channel, in the drain current, in the transconductance and in the on-state series resistance parameters.

FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs

“…So, we carefully designed the FISH layout style for improving the resultant longitudinal electrical field that yields an increase of I DS , g m , and g m /I DS , and a decrease of R DS_on when compared to the CSM counterpart considering the same bias conditions. 19 Figure 1 presents an example of the FISH SOI MOSFET (FSM) layout. 19 In Figure 1, α is the angle defined by the two metallurgical junctions composed by the drain/source and channel regions, W is the effective channel width, L is the length of the gate material that can be implemented with the minimum dimensions allowed by the manufacturing process technology, L eff is the effective channel length, − → ε 1 and − → ε 2 are the two electrical field components in the P point as a result of the application of the drain bias (perpendicular to the two metallurgical junctions between the drain and channel regions) and − → ε T is the resultant electric field (= − → ε 1 + − → ε 2 ) that is higher than the one found in the transistor with a rectangular gate shape (CSM).…”

“…19 Figure 1 presents an example of the FISH SOI MOSFET (FSM) layout. 19 In Figure 1, α is the angle defined by the two metallurgical junctions composed by the drain/source and channel regions, W is the effective channel width, L is the length of the gate material that can be implemented with the minimum dimensions allowed by the manufacturing process technology, L eff is the effective channel length, − → ε 1 and − → ε 2 are the two electrical field components in the P point as a result of the application of the drain bias (perpendicular to the two metallurgical junctions between the drain and channel regions) and − → ε T is the resultant electric field (= − → ε 1 + − → ε 2 ) that is higher than the one found in the transistor with a rectangular gate shape (CSM). 19 Additionally, note that the FISH layout style can also be applied to any other CMOS manufacturing technology of integrated circuits, either planar or three-dimensional (FinFET, Tri-Gate MOSFET, Surrounding Gate MOSFET, etc), by simply changing the gate mask.…”

“…19 Additionally, note that the FISH layout style can also be applied to any other CMOS manufacturing technology of integrated circuits, either planar or three-dimensional (FinFET, Tri-Gate MOSFET, Surrounding Gate MOSFET, etc), by simply changing the gate mask. 19 The − → ε T defines the direction of the FISH I DS . Moreover, from Figure 1, one can derive that this innovative layout, though it is manufactured with the smallest feature size allowed by the CMOS manufacturing process technology, presents an effective channel length (L eff ) higher than the one found in the conventional MOSFET counterpart, which is given by L/sin(α/2).…”

Estudo do casamento entre MOSFETs implementados com geometrias de porta não convencionais em ambientes de radiações de raios X

“…Desta forma, deve-se comparar este valor de "Fcalculado" com o valor de FC obtido da tabela de distribuição F em função do nível de significância α' e em função do número de graus de liberdade (g.l.) das amostras que têm (k-1) graus de liberdade no numerador da equação ( 26) e (n'-k) graus de liberdade no denominador da equação (26). Se "Fcalculado" for superior ao valor de FC, deve-se rejeitar a hipótese nula [52], [53], [54], [67], [66].…”

“…Deve-se ressaltar que uma possível alternativa para a implementação de MOSFETs, que não adiciona qualquer custo para o atual processo de fabricação de CIs CMOS, é a denominada de "Engenharia de Junção PN entre as regiões de Dreno-Canal e Canal-Fonte do MOSFET", que se refere ao uso de novos e diferentes estilos de leiautes de porta para a implementação de transistores que possuem formatos de porta não retangulares, ou seja, diferentemente dos MOSFETs convencionais [20]. Alguns exemplos dessas estruturas de leiaute não convencionais de porta são: SOI MOSFETs de porta em formato de Anel Circular (CGSMs) [21], [22], MOSFETs do tipo Wave (formato de porta semelhante a letra "S") [23], [24], [25] do tipo Fish [26], [27], do tipo Diamante [28], [29], do tipo Octogonal [30] e do tipo elipsoidal [31].…”