Nanocrystalline porous silicon films, which have been formed by using simple wet electrochemical etching process in HF electrolyte, were applied for passivation of high power silicon diodes. An optimal technology was designed to manufacture a uniform layer of porous silicon over the area of the p−n junction. The 8% increase in the yield was achieved on Ø100 mm diameter wafers with 69 cells of diodes in each, by using a very simple technology for the formation of porous layer for passivation of high power silicon diodes.

The procedure of wet chemical etching, which plays an important role in the fabrication of high-power Si devices in standard commercial equipment, is discussed. The characteristics of isolation grooves in Si high-voltage thyristors and diodes have been investigated, with respect to etchants and wet etching conditions. It has been found that the standard deviation in the depth values of isolation grooves produced in the Si wafer of 125 mm in diameter is reduced to 0.85 µm using a proposed modified technological procedure.