A SINGLE-CHIP PREAMPLIFIER, which used lp, NMOS that has been designed for optical fiber PIN receivers, will be reported. The device, for many applications, could replace hybrid IC (HIC) preamplifiers.The transimpedance amplifier shown in Figure 1 is of the nonintegrating type discussed earlier". Transistors M 1 through M12 provide an A0 voltage gain. The feedback resistor, Rf, is obtained by biasing M20 in the linear (triode) region.
Design Constraints and GoalsTaking sensitivity and stability requirements into account for a 44.7Mb receiver, Rf should be greater than l%OKG A0 greater than 125, bandwidth greater than 90MHz, and gate area of M20 less than 2Opm2. For this latter requirement, the transmission line properties of M20 are considered, so that the proper phase shift and closed loop stability can be assured. This places an upper limit on the maximum size (W x L) of the device resulting in a narrow (W = 1 S p ) transistor.The first stage is of the cascode type, which minimizes the Miller capacitance, with M2 acting to increase the transimpedence of M1. The noise from M1 is minimized by setting the gate capaeitance of M 1 equal to the sum of the photodiode and stray capacitances. M5 and M6 form a very wide band level shifter. M7 with load M8 and M9 with load M10 form two common source gain stages. Circuit analysis simulations predict an A0 of 300 with a bandwidth of -200MHz. These simulations predict an optical sensitivity at 44.7Mb of -50.5dBm.The amplifier was made with a fine-line, enhancement/ depletion NMOS using l.0p coded polysilicon gates resulting in an effeetive channel length of 0 . 5~ All other levels were coded using 1.5p design rules. The processed amplifier, shown in Figure 2, occupies an active area of 140h x 245p or 0.035mm2.the single pole rolloff at -17OMHz. The optical sensitivity was measured by replacing the preamplifier on a standard FT-3 regenerator board. The resulting sensitivity at a BER of 1E-7 is -47dBm (22nA of signal current) at a transimpedence setting of -3OOKa The dynamic range, without a shunt MOSFET at the input4, is 2ldBm (42dB electrical). The same device was tested on a 90Mb system and optical sensitivity is -37dBm. These chip receivers are l7dB better at 44.7Mb than earlier single-chip receivers and l l d B better at 90hTb3. However, these results are 3dB worse at 44.7Mb than discrete GaAs/bipolar ampli-fiers49'. This poorer-than-expected noise performance may be due to yet unknown noise sources present in short-channel MOSFET devices. These initial results incidate that this preamplifier has the necessary gain and bandwidth for many data link and video link applications with the potential that one design can be used for several different transmission rates. This NMOS IC realization offers potentially better sensitivity than HICs because of reduced input capacitance and w i l l allow the integration of other analog and digital regenerator functions on the same silicon chip. Open loop measurements indicate an average A0 of 180 with *A0 -Open loop voltage gain. NMOS", E...
New York, NY AN OPERATIONAL AMPLIFIER which uses an enhancement/ depletion NMOS technology has been designed for low power Consumption, low process sensitivity, large bandwidth and small area.The circuit, shown in Figure 1, features a self-biased input stage that eliminates the need for precise matching between the depletion loads M3A and M3B and the tail current source hl5. This is achieved in the following manner: h42A and M2B have one-half the width of M I A and ht1B and thus their combined current is equal to the common mode current in each of M1A and M1B. Common mode feedback through M6 and M5 results
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