A new electrochemical technique has been developed for etching platinum in the processing of silicon integrated circuits. A periodically varying potential is applied to a silicon wafer in a room temperature hydrochloric acid solution. The waveform has been designed to overcome problems associated with the passivation of the platinum surface and with the relatively high resistance of the metallization. The process has the following properties: the resolution of electroetched test patterns is good; the process is compatible with both positive and negative photoresists; the etch time is a few minutes for the platinum thicknesses commonly used in integrated circuits; the process lends itself to instrumentation for determination of the completion of platinum removal; the diss.olved platinum can be recovered. The electroetching process is also applicable to the etching of other noble metals and to the etching of metallizations on other substrates.One metallization used in the manufacture of silicon integrated circuits is titanium-platinum-gold. In one method of delineating patterns using this metallization scheme, the titanium and then the platinum are evaporated or sputtered onto the substrate; then the platinum pattern is defined by photoresist and etched. Subsequently, a new layer of photoresist is applied and gold is selectively electroplated. Finally, the exposed titanium is etched. The areas to be etched and the spacings between them may be as narrow as 5-10 #m, while the thicknesses of the platinum and titanium layers are of the order of 2000 and 1000A, respectively. There are several chemical etches for titanium that can be adequately controlled. The platinum is usually etched in hot aqua regia; however, controlling the etch rate, determining the end point, and preventing undercutting of the photoresist are serious problems.An electrolytic process is desirable because it offers numerous advantages in the areas of control, automation, and instrumentation. Raub and Buss (1) have etched the noble m'etals at significant rates using an alternating current in solutions that form complexes with these metals, for example, cyanides and chlorides. Black (2) adapted this technique to the e]ectroetching of platinum metallizations on semiconductor devices. Yahalom (3) used square potential pulses of 1 msec duration in a hydrochloric acid solution at room temperature to etch platinum wires at rates as high as 40(}0 A/min. During the anodic pulse at +I.0V (SCE) the platinum dissolves but concurrently the surface is passivated, thereby reducing the rate of dissolution. During the cathodic pulse at --0.3V, the passivating film is reduced. Yahalom showed that platinum would also etch, but at a slower rate, if a triangular potentialcontrolled waveform between the potential limits of --0.3 and -}-I.0V were used; the etch rate increased with the frequency of the waveform.In this paper we report the development of a rapid, reproducible electrolytic method for etching patterns in platinum on semiconductor slices and on other substrat...
The frequency dependence of the impedance of interface states on thermally oxidized silicon has been measured using MOS capacitors with very thin (83 Å) oxides on non‐degenerate p‐type silicon. Frequency response of the capacitance and conductance was measured from 10 Hz to 50 MHz at 142, 178, and 220 °K. The frequency response deviates significantly from that predicted by the Shockley‐Read‐Hall model applied to interface states. The high‐frequency portion of the frequency response can be explained by the SRH theory if it is assumed that there exists a variation of oxide charge concentration over the area of the device. At low frequencies the conductance can be explained by a two‐step model consisting of the SRH process plus elastic tunneling between interface states and traps located in the oxide. This model was previously employed by Fu and Sah in connection with I/f noise. The two‐step model, modified to account for areal variation of oxide charge concentration, explains the observed frequency response at all three temperatures over six decades of frequency.
Fast surface states at the silicon-silicon dioxide interface have been studied using the MOS capacitor structure with a very thin oxide (50–100 Å), which greatly enhances the effect of the surface states on the capacitance-voltage characteristics. On p-type silicon, a surface-state distribution with a peak at 0.3 eV above the valence band is observed. Comparison of the experimental results with theoretical calculations based on the equivalent circuit model is made. Total density of state of 5.4×1012/cm2 with a peak of 3×1013 surface states/cm2 eV are observed.
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