Solitons are nonlinear waves present in diverse physical systems including plasmas, water surfaces and optics. In silicon, the presence of two photon absorption and accompanying free carriers strongly perturb the canonical dynamics of optical solitons. Here we report the first experimental demonstration of soliton-effect pulse compression of picosecond pulses in silicon, despite two photon absorption and free carriers. Here we achieve compression of 3.7 ps pulses to 1.6 ps with o10 pJ energy. We demonstrate a B1-ps free-carrier-induced pulse acceleration and show that picosecond input pulses are critical to these observations. These experiments are enabled by a dispersion-engineered slow-light photonic crystal waveguide and an ultra-sensitive frequency-resolved electrical gating technique to detect the ultralow energies in the nanostructured device. Strong agreement with a nonlinear Schrö-dinger model confirms the measurements. These results further our understanding of nonlinear waves in silicon and open the way to soliton-based functionalities in complementary metal-oxide-semiconductor-compatible platforms.

Nonlinear silicon photonics will play an important role in future integrated opto-electronic circuits. Here we report temporal pulse broadening induced by the dynamic interplay of nonlinear free-carrier dispersion coupled with group-velocity dispersion in nanostructured silicon waveguides for the first time, to the best of our knowledge. Further, we demonstrate that the nonlinear temporal dynamics are supported or countered by third-order dispersion, depending on the sign. Our time-domain measurements of the subpicojoule pulse dynamics are supported by strong agreement with numerical modeling. In addition to the fundamental nonlinear optical processes unveiled here, these results highlight dispersion engineering as a powerful tool for controlling free-carrier temporal effects.

The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices.Index Terms-CMOS integrated circuits, metrology, strain measurement.

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