An analog front-end (AFE) for Electrocardiogram (ECG) monitoring with built-in compressed sensing (CS) is presented. The CS is incorporated into an array of incremental ADCs, and the power overhead is minimized through segmented CS and dynamic bias control. A decompression technique is also presented to enhance the effective resolution of CS by 1b without degrading the compression ratio (CR). This AFE, fabricated in a 0.11μm CMOS process, compresses data by 78/56% with a 7/8b resolution, and consumes only 9μA from a 1V supply.
Abstrocf-This paper presents a dual-band receiver front-end architecture which combines the dual-conversion [4] and half-IF techniques for IEEE 802.1laibig. The proposed architecture receives dual-band signal with single receiver chain to reduce components count such as the down-conversion mixer and VCO. The required LO frequencies of the dual-band application can be synthesized by only one VCO in combination with a divide-by-four circuit. An LC tank aided mechanism of mixer is also proposed to deal with the flicker noise. The core portion of the front-end receiver has been fabricated in 1P6M 0.18pm CMOS technology. The delivered gain, noise figure, and IIP3 are 20 dB, 3.5 dB, and -13 dBm, respectively simulated. The chip occupies an area of 1.21x1.46mm' and the power consumption is 24mW under the supply voltage of 1.8V.
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