Abstrocf-This paper presents a dual-band receiver front-end architecture which combines the dual-conversion [4] and half-IF techniques for IEEE 802.1laibig. The proposed architecture receives dual-band signal with single receiver chain to reduce components count such as the down-conversion mixer and VCO. The required LO frequencies of the dual-band application can be synthesized by only one VCO in combination with a divide-by-four circuit. An LC tank aided mechanism of mixer is also proposed to deal with the flicker noise. The core portion of the front-end receiver has been fabricated in 1P6M 0.18pm CMOS technology. The delivered gain, noise figure, and IIP3 are 20 dB, 3.5 dB, and -13 dBm, respectively simulated. The chip occupies an area of 1.21x1.46mm' and the power consumption is 24mW under the supply voltage of 1.8V.
This paper presents a sampling frequency offset estimation in time domain for discrete multitone (DMT) systems. Cyclic prefix (CP) enables this estimation without pilots. The proposed algorithm realizes sampling frequency estimation on each sample within the last period where the CP copied from. The sampling-rate iteration method markedly improves acquisition speed and jitter performances. Simulations show that this method can synchronize DMT systems in both AWGN channels and twisted pair copper wires along with non-ideal factors. Practical examples of the veryhigh bit-rate digital subscriber lines (VDSL) are used to illustrate results.I.
AbslmcI-This paper presents a hardware efficient VLSl design of digital baseband for 64-QAM communication systems over the lastmile cable network. This VLSI system design involves a mt-efficient architecNre of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which d u c e the hardware requirement by a factor of four comparing with traditional quadrsture d i m t form FIR filters. In this design, the two.fold carrier recovery Imp possesses a pull-in range of i l O O k H z (i.e. f18,500ppm of the symbol rate) and -82dBc jitter suppr?ssion. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizer the symbol spaced timing recovery in a i200ppn tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mbls 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35pm CMOS technology, the transceiver design occupies a chip area 5.5mm x 5.5mm and power consumption 1.35W (1.OW for RX) when the power supply is 3.3V.
This paper proposes a two-fold carrier recovery loop that possesses f25000-ppm pull-in range and 7-ms acquisition time for 64-QAM blind adaptive system. The carrier recovery system contains a prior wide-band loop to acquire a coarse carrier frequency and a posterior narrow-band loop to achieve -82dBc jitter suppression. It can be applied to a 4.035-MHz low-IF cable modem system with the f100-kHz frequency offset tolerance requirement. The two-fold camer recovery loop operates in consecutive three stages, which are Costas carrier phase estimation, DDML camer phase estimation, and DD-MMSE carrier phase estimation. The proposed architecture is hardware efficient since the three-staged operation shares most of the circuit functions.
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