Extending the resolution and spatial proximity of lithographic patterning below critical dimensions of 20 nm remains a key challenge with very-large-scale integration, especially if the persistent scaling of silicon electronic devices is sustained. One approach, which relies upon the directed self-assembly of block copolymers by chemical-epitaxy, is capable of achieving high density 1 : 1 patterning with critical dimensions approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating high areal density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer nanopatterns with a L(0) (pitch) of 42 nm, on chemically pre-patterned surfaces. Parallel arrays (5 × 10(6) wires per cm) of uni-directional and isolated silicon nanowires on insulator substrates with critical dimension ranging from 15 to 19 nm were fabricated by using precision plasma etch processes; with each stage monitored by electron microscopy. This step-by-step approach provides detailed information on interfacial oxide formation at the device silicon layer, the polystyrene profile during plasma etching, final critical dimension uniformity and line edge roughness variation nanowire during processing. The resulting silicon-nanowire array devices exhibit Schottky-type behaviour and a clear field-effect. The measured values for resistivity and specific contact resistance were ((2.6 ± 1.2) × 10(5)Ωcm) and ((240 ± 80) Ωcm(2)) respectively. These values are typical for intrinsic (un-doped) silicon when contacted by high work function metal albeit counterintuitive as the resistivity of the starting wafer (∼10 Ωcm) is 4 orders of magnitude lower. In essence, the nanowires are so small and consist of so few atoms, that statistically, at the original doping level each nanowire contains less than a single dopant atom and consequently exhibits the electrical behaviour of the un-doped host material. Moreover this indicates that the processing successfully avoided unintentional doping. Therefore our approach permits tuning of the device steps to contact the nanowires functionality through careful selection of the initial bulk starting material and/or by means of post processing steps e.g. thermal annealing of metal contacts to produce high performance devices. We envision that such a controllable process, combined with the precision patterning of the aligned block copolymer nanopatterns, could prolong the scaling of nanoelectronics and potentially enable the fabrication of dense, parallel arrays of multi-gate field effect transistors.
The use of a metallic adhesion layer is known to increase the thermomechanical stability of Au thin films against solid-state dewetting, but in turn results in damping of the plasmonic response, reducing their utility in applications such as heatassisted magnetic recording (HAMR). In this work, 50 nm Au films with Ti adhesion layers ranging in thickness from 0 to 5 nm were fabricated, and their thermal stability, electrical resistivity, and plasmonic response were measured. Subnanometer adhesion layers are demonstrated to significantly increase the stability of the thin films against dewetting at elevated temperatures (>200 °C), compared to more commonly used adhesion layer thicknesses that are in the range of 2−5 nm. For adhesion layers thicker than 1 nm, the diffusion of excess Ti through Au grain boundaries and subsequent oxidation was determined to result in degradation of the film. This mechanism was confirmed using transmission electron microscopy and X-ray photoelectron spectroscopy on annealed 0.5 and 5 nm adhesion layer samples. The superiority of subnanometer adhesion layers was further demonstrated through measurements of the surface-plasmon polariton resonance; those with thinner adhesion layers possessed both a stronger and spectrally sharper resonance. These results have relevance beyond HAMR to all Ti/Au systems operating at elevated temperatures.
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