We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trapassisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS = −0.5 V, good short-channel effect control, and high transconductance (g m = 1.2 mS/µm at V DS = −1 V and 1.05 mS/µm at V DS = −0.5 V for L G = 70 nm). The Ge FinFET presented in this paper exhibits the highest g m /SS sat at V DD = 1 V reported for nonplanar unstrained Ge p-FETs to date.Index Terms-Aspect ratio trapping (ART), band-to-band tunneling (BTBT), epitaxy, FinFET, germanium, scaling, trap-assisted tunneling (TAT).
In this paper, we study a new class of two-dimensional codes, here called multilevel prime codes, with expanded code cardinality by relaxing the maximum cross-correlation function to any arbitrary positive integer. Besides having asymptotically optimal cardinality and zero autocorrelation sidelobes, these multilevel prime codes can be partitioned into a tree structure of multiple levels of subsets of code matrices. In each level, the number of subsets, the number of code matrices per subset, and the cross-correlation function of each subset are related to the level number. The performance of the new codes in an optical code-division multiple-access system with hard-limiting detection is analyzed. Our results show that the unique partition property of the multilevel prime codes supports a trade-off between code cardinality and performance for meeting different system requirements, such as user capacity and throughput
The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.
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