In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.

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Dielectric breakdown is the process of local materials transiting from insulating to conductive when the dielectric is submerged in a high external electric field environment. We show that the atomistic changes of the chemical bonding in a nanoscale breakdown path are extensive and irreversible. Oxygen atoms in dielectric SiO2 are washed out with substoichiometric silicon oxide (SiOx with x<2) formation, and local energy gap lowering with intermediate bonding state of silicon atoms (Si1+, Si2+, and Si3+) in the percolation leakage path. Oxygen deficiency within the breakdown path is estimated to be as high as 50%–60%.

Articles you may be interested inModel for the voltage and temperature dependence of the soft breakdown current in ultrathin gate oxides A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy ͑DBIE͒ formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 Å and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

The wetting reaction between molten eutectic SnPb solder and a sputtered trilayer Cu/Ni(V)/Al thin film metallization was studied using cross-sectional transmission electron microscopy and scanning electron microscopy. Reaction temperatures were from 200 to 240 °C and reaction times ranged from 1 to 40 min. The initial reaction products were Cu6Sn5 and Cu3Sn. The latter transforms to the former after an annealing greater than 1 min at 220 °C. The Cu6Sn5 grains adhere well to the Ni(V) surface and no spalling of them was observed, even after 40 min at 220 °C. This surprising result indicates that the Cu/Ni(V)/Al or Cu6Sn5/Ni(V)/Al is a stable thin film metallization for low temperature eutectic SnPb solder direct chip attachment to organic substrates. Additionally, Kirkendall voids accompanied Cu3Sn formation, yet the voids disappear when the Cu3Sn transforms to Cu6Sn5.

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Vertically aligned carbon nanofibers (CNFs) grown by plasma enhanced chemical vapor deposition (PECVD) were transformed into cone-shaped nanostructures after treatment by argon (Ar) plasma. Significant enhancement of field emission characteristics of the post-treated CNFs has been achieved. Analysis by electron microscopy and energy dispersive spectroscopy (EDS) suggests that the structural transformation is a result of a cosputtering∕deposition process by energetic plasma ions. The enhancements can be attributed to the combining effects of an additional Si∕C layer coverage, catalytic nanoparticles removal and the sharpening of CNFs tips. The argon plasma post-treatment processes developed here can be easily extended to in situ PECVD processes for fabricating CNFs based emitters.