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5d transition metal Pt is the canonical spin Hall material for efficient generation of spin−orbit torques (SOTs) in Pt/ferromagnetic layer (FM) heterostructures. However, for a long while with tremendous engineering endeavors, the damping-like SOT efficiencies (ξ DL ) of Pt and Pt alloys have still been limited to ξ DL < 0.5. Here we present that with proper alloying elements, particularly 3d transition metals V and Cr, a high spin−orbital Hall conductivity (σ SH ≈ 6.5 × 10 5 (ℏ/2e) Ω −1 m −1 ) can be developed. Especially for the Cr-doped case, an extremely high ξ DL ≈ 0.9 in a Pt 0.69 Cr 0.31 / Co device can be achieved with a moderate Pt 0.69 Cr 0.31 resistivity of ρ xx ≈ 133 μΩ cm. A low critical SOT-driven switching current density of J c ≈ 3.2 × 10 6 A cm −2 is also demonstrated. The damping constant (α) of the Pt 0.69 Cr 0.31 /FM structure is also found to be reduced to 0.052 from the pure Pt/FM case of 0.078. The overall high σ SH , giant ξ DL , moderate ρ xx , and reduced α of such a Pt−Cr/FM heterostructure makes it promising for versatile extremely low power consumption SOT memory applications.

High spin-orbit torques (SOTs) generated by topological materials and heavy metals interfaced with a ferromagnetic layer show promise for next generation magnetic memory and logic devices. SOTs generated from the in-plane spin polarization along y-axis originated by the spin Hall and Edelstein effects can switch magnetization collinear with the spin polarization in the absence of external magnetic fields. However, an external magnetic field is required to switch the magnetization along x and z-axes via SOT generated by y-spin polarization. Here, we present that the above limitation can be circumvented by unconventional SOT in magnetron-sputtered thin film MnPd 3 . In

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We propose a new power simulation technique that effectively considers dynamic program execution behaviors such as cache hit/miss or branch predicted/mis-predicted and achieves fast and accurate power estimation results. Traditionally, accurate software power estimation relies on slower fine-grained simulations while faster coarse-grained simulations often lead to inaccurate estimation results. We pre-characterize detailed circuit power consumption, pipeline and branch effects of each basic block for accuracy and then apply efficient instruction-set simulators to compute total software power consumption. The experimental result shows that our approach achieves over 200 MIPS performance with a less than 3% error rate.