Energy Efficient Computing With High-Density, Field-Free STT-Assisted SOT-MRAM (SAS-MRAM)

Hwang, William; Xue, Fen; Zhang, Fan; Song, Ming; Lee, Chien-Min; Turgut, Emrah; Chen, T. C.; Bao, Xinyu; Tsai, W.; Fan, Deliang; Wang, Shan X.

doi:10.1109/tmag.2022.3224729

Cited by 4 publications

(3 citation statements)

References 30 publications

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“…Spintronic devices provide non-volatile data storage, low read and write energy, high write endurance, and back-end-ofthe-line compatibility with a CMOS fabrication process [2]. As a result of these properties, spintronics has emerged as a unique platform for dense data storage, digital and analog in-memory computing, neuromorphic computing, normally-off computing, and new, efficient implementations of digital logic [3][4][5][6][7][8][9]. On the reliability side, non-volatile logic gates enable rapid recovery from transient power losses.…”

Section: Introductionmentioning

confidence: 99%

Parallel Matrix Multiplication Using Voltage-Controlled Magnetic Anisotropy Domain Wall Logic

Nicholas

Liu

Bennett

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device that can simultaneously store data and perform computations. These three-terminal devices are promising for digital logic due to their nonvolatility, low-energy operation, and radiation hardness. Here, we augment the DW-MTJ logic gate with voltage controlled magnetic anisotropy (VCMA) to improve the reliability of logical concatenation in the presence of realistic process variations. VCMA creates potential wells that allow for reliable and repeatable localization of domain walls. The DW-MTJ logic gate supports different fanouts, allowing for multiple inputs and outputs for a single device without affecting area. We simulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) with 4-bit and 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates to enable fine-grained pipelining and high parallelism. The DW-MTJ systolic array provides comparable throughput and efficiency to state-of-the-art CMOS systolic arrays while being radiation-hard. These results improve the feasibility of using domain wall-based processors, especially for extreme-environment applications such as space.

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Section: Introductionmentioning

confidence: 99%

Parallel Matrix Multiplication Using Voltage-Controlled Magnetic Anisotropy Domain Wall Logic

Nicholas

Liu

Bennett

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…One of the issues with SOT-MRAM is the large bit-cell area arising due to the presence of separate read and write transistors. To reduce the cell footprint of SOT-MRAM, works have been done on sharing SOT channel among multiple magnetic tunnel junctions (MTJs) using spin-transfer torque (STT) 12 or voltage-controlled magnetic anisotropy (VCMA) effect. 13,14 However, detailed study of various trade-offs in such schemes while maintaining low write error rate (WER) and adequate selectivity is lacking.…”

Section: Introductionmentioning

confidence: 99%

Modeling of spin-orbit torque (SOT) channel and high-density SOT magnetic random-access memory

Kumar,

Naeemi

2023

Spintronics XVI

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Spin-orbit torque (SOT) devices are being pursued for various memory and in-memory compute applications. At nanoscale dimensions, electric current flowing through the SOT channel can be non-uniform due to incomplete current redistribution. Such effects were ignored in the prior modeling works. We present a comprehensive modeling framework for SOT devices that capture the effects of incomplete current redistribution along with interface spin-mixing, and non-uniform resistivity. Our transfer matrix-based formalism along with finite element simulations can account for any local variation in resistivity and spin diffusion length along with accounting for various spin-scattering mechanisms. In addition, we quantify the optimal SOT layer thickness to minimize the write energy in terms of its resistivity and spin diffusion length. To improve the bit density of SOT magnetic random-access memory (MRAM), we explore area saving schemes based on sharing SOT channel among multiple magnetic tunnel junctions (MTJs) with the help of voltage-controlled magnetic anisotropy (VCMA) effect and spin-transfer torque (STT). Using micromagnetic simulations, we study various tradeoffs among write time, current, error rate, and the number of MTJs. Our results show that the number of MTJs on the shared SOT channel is limited by the voltage drop over the SOT channel and write error rate, and having more than 4 MTJs on a SOT channel poses major challenges in terms of reliability.

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“…Piyush Kumar and Azad Naeemi are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA, email: pkumar315@gatech.edu. magnetic tunnel junctions (MTJs) with the help of STT [6] or voltage-controlled magnetic anisotropy (VCMA) effect [7], [8]. However, such schemes would require many trade-offs and a detailed evaluations of such schemes that proves low write error-rates and adequate selectivity accounting for thermal noise, variability, and the IR-drop on the SOT layer are missing.…”

Section: Introductionmentioning

confidence: 99%

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

Kumar

Naeemi

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper explores an area saving scheme for spinorbit torque (SOT) magnetic random-access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs; voltage-controlled magnetic anisotropy (VCMA) assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT) assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various tradeoffs among write current, time and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than 4 MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.Index Terms-Magnetic random-access memory (MRAM), spin-transfer torque (STT), spin-orbit torque (SOT), voltagecontrolled magnetic anisotropy (VCMA).

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Energy Efficient Computing With High-Density, Field-Free STT-Assisted SOT-MRAM (SAS-MRAM)

Cited by 4 publications

References 30 publications

Parallel Matrix Multiplication Using Voltage-Controlled Magnetic Anisotropy Domain Wall Logic

Parallel Matrix Multiplication Using Voltage-Controlled Magnetic Anisotropy Domain Wall Logic

Modeling of spin-orbit torque (SOT) channel and high-density SOT magnetic random-access memory

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

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